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[PATCH] sky2: remove pci-express hacks
Eliminate special case tuning for PCI-Express. This code causes receive hangs and doesn't help performance much anyway. Signed-off-by: Stephen Hemminger <shemmnger@osdl.org> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
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@ -651,12 +651,12 @@ static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, size_t len)
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}
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/* Setup Bus Memory Interface */
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static void sky2_qset(struct sky2_hw *hw, u16 q, u32 wm)
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static void sky2_qset(struct sky2_hw *hw, u16 q)
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{
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sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
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sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
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sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
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sky2_write32(hw, Q_ADDR(q, Q_WM), wm);
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sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
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}
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/* Setup prefetch unit registers. This is the interface between
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@ -921,7 +921,7 @@ static int sky2_rx_start(struct sky2_port *sky2)
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int i;
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sky2->rx_put = sky2->rx_next = 0;
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sky2_qset(hw, rxq, is_pciex(hw) ? 0x80 : 0x600);
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sky2_qset(hw, rxq);
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sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
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rx_set_checksum(sky2);
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@ -1004,7 +1004,7 @@ static int sky2_up(struct net_device *dev)
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sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
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RB_RST_SET);
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sky2_qset(hw, txqaddr[port], 0x600);
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sky2_qset(hw, txqaddr[port]);
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if (hw->chip_id == CHIP_ID_YUKON_EC_U)
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sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
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@ -2148,20 +2148,6 @@ static int sky2_reset(struct sky2_hw *hw)
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sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
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}
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if (is_pciex(hw)) {
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u16 pctrl;
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/* change Max. Read Request Size to 2048 bytes */
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pci_read_config_word(hw->pdev, PEX_DEV_CTRL, &pctrl);
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pctrl &= ~PEX_DC_MAX_RRS_MSK;
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pctrl |= PEX_DC_MAX_RD_RQ_SIZE(4);
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sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
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pci_write_config_word(hw->pdev, PEX_DEV_CTRL, pctrl);
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sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
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}
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sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
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spin_lock_bh(&hw->phy_lock);
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@ -631,6 +631,8 @@ enum {
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BMU_CLR_RESET = BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR,
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BMU_OPER_INIT = BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START |
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BMU_FIFO_ENA | BMU_OP_ON,
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BMU_WM_DEFAULT = 0x600,
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};
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/* Tx BMU Control / Status Registers (Yukon-2) */
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