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[POWERPC] Update booting-without-of for Freescale PCIe MSI
Binding document adding for Freescale PCIe MSI support. Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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@ -57,7 +57,10 @@ Table of Contents
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n) 4xx/Axon EMAC ethernet nodes
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n) 4xx/Axon EMAC ethernet nodes
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o) Xilinx IP cores
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o) Xilinx IP cores
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p) Freescale Synchronous Serial Interface
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p) Freescale Synchronous Serial Interface
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q) USB EHCI controllers
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q) USB EHCI controllers
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r) Freescale Display Interface Unit
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s) Freescale on board FPGA
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t) Freescael MSI interrupt controller
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VII - Marvell Discovery mv64[345]6x System Controller chips
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VII - Marvell Discovery mv64[345]6x System Controller chips
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1) The /system-controller node
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1) The /system-controller node
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@ -2870,6 +2873,44 @@ platforms are moved over to use the flattened-device-tree model.
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reg = <0xe8000000 32>;
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reg = <0xe8000000 32>;
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};
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};
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t) Freescale MSI interrupt controller
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Reguired properities:
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- compatible : compatible list, contains 2 entries,
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first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
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etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending on
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the parent type.
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- reg : should contain the address and the length of the shared message
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interrupt register set.
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- msi-available-ranges: use <start count> style section to define which
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msi interrupt can be used in the 256 msi interrupts. This property is
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optional, without this, all the 256 MSI interrupts can be used.
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- interrupts : each one of the interrupts here is one entry per 32 MSIs,
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and routed to the host interrupt controller. the interrupts should
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be set as edge sensitive.
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- interrupt-parent: the phandle for the interrupt controller
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that services interrupts for this device. for 83xx cpu, the interrupts
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are routed to IPIC, and for 85xx/86xx cpu the interrupts are routed
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to MPIC.
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Example
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msi@41600 {
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compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
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reg = <0x41600 0x80>;
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msi-available-ranges = <0 0x100>;
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interrupts = <
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0xe0 0
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0xe1 0
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0xe2 0
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0xe3 0
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0xe4 0
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0xe5 0
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0xe6 0
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0xe7 0>;
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interrupt-parent = <&mpic>;
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};
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VII - Marvell Discovery mv64[345]6x System Controller chips
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VII - Marvell Discovery mv64[345]6x System Controller chips
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===========================================================
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===========================================================
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