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i2c: nomadik: rename private struct pointers from dev to priv
Disambiguate the usage of dev as a variable name; it is usually best to keep it reserved for struct device pointers. Avoid having multiple names for the same struct pointer (previously: dev, nmk, nmk_i2c). Fix whitespace code style; return indented twice, spacing besides infix operators, align function call arguments to opening parenthesis. Remove useless cast to unused return value from init_hw(). Introduce local dev variable in probe() to alias &adev->dev. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andi Shyti <andi.shyti@kernel.org> Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
This commit is contained in:
Théo Lebrun
Andi Shyti
parent
1b9a8e8af0
commit
ae9977eefc
@ -206,12 +206,12 @@ static inline void i2c_clr_bit(void __iomem *reg, u32 mask)
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/**
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* flush_i2c_fifo() - This function flushes the I2C FIFO
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* @dev: private data of I2C Driver
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* @priv: private data of I2C Driver
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*
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* This function flushes the I2C Tx and Rx FIFOs. It returns
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* 0 on successful flushing of FIFO
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*/
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static int flush_i2c_fifo(struct nmk_i2c_dev *dev)
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static int flush_i2c_fifo(struct nmk_i2c_dev *priv)
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{
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#define LOOP_ATTEMPTS 10
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int i;
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@ -224,19 +224,19 @@ static int flush_i2c_fifo(struct nmk_i2c_dev *dev)
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* bits, until then no one must access Tx, Rx FIFO and
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* should poll on these bits waiting for the completion.
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*/
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writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR);
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writel((I2C_CR_FTX | I2C_CR_FRX), priv->virtbase + I2C_CR);
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for (i = 0; i < LOOP_ATTEMPTS; i++) {
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timeout = jiffies + dev->adap.timeout;
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timeout = jiffies + priv->adap.timeout;
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while (!time_after(jiffies, timeout)) {
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if ((readl(dev->virtbase + I2C_CR) &
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if ((readl(priv->virtbase + I2C_CR) &
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(I2C_CR_FTX | I2C_CR_FRX)) == 0)
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return 0;
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return 0;
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}
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}
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dev_err(&dev->adev->dev,
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dev_err(&priv->adev->dev,
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"flushing operation timed out giving up after %d attempts",
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LOOP_ATTEMPTS);
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@ -245,45 +245,45 @@ static int flush_i2c_fifo(struct nmk_i2c_dev *dev)
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/**
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* disable_all_interrupts() - Disable all interrupts of this I2c Bus
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* @dev: private data of I2C Driver
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* @priv: private data of I2C Driver
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*/
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static void disable_all_interrupts(struct nmk_i2c_dev *dev)
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static void disable_all_interrupts(struct nmk_i2c_dev *priv)
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{
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u32 mask = IRQ_MASK(0);
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writel(mask, dev->virtbase + I2C_IMSCR);
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writel(mask, priv->virtbase + I2C_IMSCR);
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}
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/**
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* clear_all_interrupts() - Clear all interrupts of I2C Controller
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* @dev: private data of I2C Driver
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* @priv: private data of I2C Driver
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*/
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static void clear_all_interrupts(struct nmk_i2c_dev *dev)
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static void clear_all_interrupts(struct nmk_i2c_dev *priv)
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{
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u32 mask;
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mask = IRQ_MASK(I2C_CLEAR_ALL_INTS);
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writel(mask, dev->virtbase + I2C_ICR);
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writel(mask, priv->virtbase + I2C_ICR);
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}
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/**
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* init_hw() - initialize the I2C hardware
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* @dev: private data of I2C Driver
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* @priv: private data of I2C Driver
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*/
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static int init_hw(struct nmk_i2c_dev *dev)
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static int init_hw(struct nmk_i2c_dev *priv)
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{
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int stat;
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stat = flush_i2c_fifo(dev);
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stat = flush_i2c_fifo(priv);
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if (stat)
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goto exit;
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/* disable the controller */
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i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
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i2c_clr_bit(priv->virtbase + I2C_CR, I2C_CR_PE);
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disable_all_interrupts(dev);
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disable_all_interrupts(priv);
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clear_all_interrupts(dev);
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clear_all_interrupts(priv);
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dev->cli.operation = I2C_NO_OPERATION;
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priv->cli.operation = I2C_NO_OPERATION;
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exit:
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return stat;
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@ -294,15 +294,15 @@ exit:
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/**
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* load_i2c_mcr_reg() - load the MCR register
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* @dev: private data of controller
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* @priv: private data of controller
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* @flags: message flags
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*/
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static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev, u16 flags)
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static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *priv, u16 flags)
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{
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u32 mcr = 0;
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unsigned short slave_adr_3msb_bits;
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mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1);
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mcr |= GEN_MASK(priv->cli.slave_adr, I2C_MCR_A7, 1);
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if (unlikely(flags & I2C_M_TEN)) {
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/* 10-bit address transaction */
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@ -313,7 +313,7 @@ static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev, u16 flags)
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* the extension (MSB bits) of the 7 bit address loaded
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* in A7
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*/
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slave_adr_3msb_bits = (dev->cli.slave_adr >> 7) & 0x7;
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slave_adr_3msb_bits = (priv->cli.slave_adr >> 7) & 0x7;
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mcr |= GEN_MASK(slave_adr_3msb_bits, I2C_MCR_EA10, 8);
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} else {
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@ -325,40 +325,40 @@ static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev, u16 flags)
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mcr |= GEN_MASK(0, I2C_MCR_SB, 11);
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/* check the operation, master read/write? */
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if (dev->cli.operation == I2C_WRITE)
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if (priv->cli.operation == I2C_WRITE)
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mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0);
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else
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mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0);
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/* stop or repeated start? */
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if (dev->stop)
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if (priv->stop)
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mcr |= GEN_MASK(1, I2C_MCR_STOP, 14);
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else
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mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14));
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mcr |= GEN_MASK(dev->cli.count, I2C_MCR_LENGTH, 15);
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mcr |= GEN_MASK(priv->cli.count, I2C_MCR_LENGTH, 15);
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return mcr;
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}
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/**
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* setup_i2c_controller() - setup the controller
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* @dev: private data of controller
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* @priv: private data of controller
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*/
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static void setup_i2c_controller(struct nmk_i2c_dev *dev)
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static void setup_i2c_controller(struct nmk_i2c_dev *priv)
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{
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u32 brcr1, brcr2;
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u32 i2c_clk, div;
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u32 ns;
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u16 slsu;
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writel(0x0, dev->virtbase + I2C_CR);
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writel(0x0, dev->virtbase + I2C_HSMCR);
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writel(0x0, dev->virtbase + I2C_TFTR);
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writel(0x0, dev->virtbase + I2C_RFTR);
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writel(0x0, dev->virtbase + I2C_DMAR);
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writel(0x0, priv->virtbase + I2C_CR);
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writel(0x0, priv->virtbase + I2C_HSMCR);
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writel(0x0, priv->virtbase + I2C_TFTR);
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writel(0x0, priv->virtbase + I2C_RFTR);
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writel(0x0, priv->virtbase + I2C_DMAR);
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i2c_clk = clk_get_rate(dev->clk);
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i2c_clk = clk_get_rate(priv->clk);
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/*
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* set the slsu:
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@ -373,7 +373,7 @@ static void setup_i2c_controller(struct nmk_i2c_dev *dev)
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* slsu = cycles / (1000000000 / f) + 1
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*/
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ns = DIV_ROUND_UP_ULL(1000000000ULL, i2c_clk);
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switch (dev->sm) {
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switch (priv->sm) {
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case I2C_FREQ_MODE_FAST:
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case I2C_FREQ_MODE_FAST_PLUS:
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slsu = DIV_ROUND_UP(100, ns); /* Fast */
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@ -388,15 +388,15 @@ static void setup_i2c_controller(struct nmk_i2c_dev *dev)
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}
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slsu += 1;
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dev_dbg(&dev->adev->dev, "calculated SLSU = %04x\n", slsu);
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writel(slsu << 16, dev->virtbase + I2C_SCR);
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dev_dbg(&priv->adev->dev, "calculated SLSU = %04x\n", slsu);
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writel(slsu << 16, priv->virtbase + I2C_SCR);
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/*
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* The spec says, in case of std. mode the divider is
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* 2 whereas it is 3 for fast and fastplus mode of
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* operation. TODO - high speed support.
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*/
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div = (dev->clk_freq > I2C_MAX_STANDARD_MODE_FREQ) ? 3 : 2;
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div = (priv->clk_freq > I2C_MAX_STANDARD_MODE_FREQ) ? 3 : 2;
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/*
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* generate the mask for baud rate counters. The controller
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@ -406,10 +406,10 @@ static void setup_i2c_controller(struct nmk_i2c_dev *dev)
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* so set brcr1 to 0.
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*/
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brcr1 = 0 << 16;
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brcr2 = (i2c_clk/(dev->clk_freq * div)) & 0xffff;
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brcr2 = (i2c_clk / (priv->clk_freq * div)) & 0xffff;
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/* set the baud rate counter register */
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writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
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writel((brcr1 | brcr2), priv->virtbase + I2C_BRCR);
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/*
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* set the speed mode. Currently we support
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@ -417,125 +417,124 @@ static void setup_i2c_controller(struct nmk_i2c_dev *dev)
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* TODO - support for fast mode plus (up to 1Mb/s)
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* and high speed (up to 3.4 Mb/s)
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*/
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if (dev->sm > I2C_FREQ_MODE_FAST) {
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dev_err(&dev->adev->dev,
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if (priv->sm > I2C_FREQ_MODE_FAST) {
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dev_err(&priv->adev->dev,
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"do not support this mode defaulting to std. mode\n");
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brcr2 = i2c_clk / (I2C_MAX_STANDARD_MODE_FREQ * 2) & 0xffff;
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writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
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writel((brcr1 | brcr2), priv->virtbase + I2C_BRCR);
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writel(I2C_FREQ_MODE_STANDARD << 4,
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dev->virtbase + I2C_CR);
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priv->virtbase + I2C_CR);
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}
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writel(dev->sm << 4, dev->virtbase + I2C_CR);
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writel(priv->sm << 4, priv->virtbase + I2C_CR);
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/* set the Tx and Rx FIFO threshold */
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writel(dev->tft, dev->virtbase + I2C_TFTR);
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writel(dev->rft, dev->virtbase + I2C_RFTR);
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writel(priv->tft, priv->virtbase + I2C_TFTR);
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writel(priv->rft, priv->virtbase + I2C_RFTR);
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}
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/**
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* read_i2c() - Read from I2C client device
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* @dev: private data of I2C Driver
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* @priv: private data of I2C Driver
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* @flags: message flags
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*
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* This function reads from i2c client device when controller is in
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* master mode. There is a completion timeout. If there is no transfer
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* before timeout error is returned.
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*/
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static int read_i2c(struct nmk_i2c_dev *dev, u16 flags)
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static int read_i2c(struct nmk_i2c_dev *priv, u16 flags)
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{
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int status = 0;
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u32 mcr, irq_mask;
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unsigned long timeout;
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mcr = load_i2c_mcr_reg(dev, flags);
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writel(mcr, dev->virtbase + I2C_MCR);
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mcr = load_i2c_mcr_reg(priv, flags);
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writel(mcr, priv->virtbase + I2C_MCR);
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/* load the current CR value */
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writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
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dev->virtbase + I2C_CR);
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writel(readl(priv->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
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priv->virtbase + I2C_CR);
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/* enable the controller */
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i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
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i2c_set_bit(priv->virtbase + I2C_CR, I2C_CR_PE);
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init_completion(&dev->xfer_complete);
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init_completion(&priv->xfer_complete);
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/* enable interrupts by setting the mask */
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irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF |
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I2C_IT_MAL | I2C_IT_BERR);
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if (dev->stop || !dev->vendor->has_mtdws)
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if (priv->stop || !priv->vendor->has_mtdws)
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irq_mask |= I2C_IT_MTD;
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else
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irq_mask |= I2C_IT_MTDWS;
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irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
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writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
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dev->virtbase + I2C_IMSCR);
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writel(readl(priv->virtbase + I2C_IMSCR) | irq_mask,
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priv->virtbase + I2C_IMSCR);
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timeout = wait_for_completion_timeout(
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&dev->xfer_complete, dev->adap.timeout);
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&priv->xfer_complete, priv->adap.timeout);
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if (timeout == 0) {
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/* Controller timed out */
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dev_err(&dev->adev->dev, "read from slave 0x%x timed out\n",
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dev->cli.slave_adr);
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dev_err(&priv->adev->dev, "read from slave 0x%x timed out\n",
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priv->cli.slave_adr);
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status = -ETIMEDOUT;
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}
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return status;
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}
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static void fill_tx_fifo(struct nmk_i2c_dev *dev, int no_bytes)
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static void fill_tx_fifo(struct nmk_i2c_dev *priv, int no_bytes)
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{
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int count;
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for (count = (no_bytes - 2);
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(count > 0) &&
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(dev->cli.count != 0);
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(priv->cli.count != 0);
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count--) {
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/* write to the Tx FIFO */
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writeb(*dev->cli.buffer,
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dev->virtbase + I2C_TFR);
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dev->cli.buffer++;
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dev->cli.count--;
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dev->cli.xfer_bytes++;
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writeb(*priv->cli.buffer, priv->virtbase + I2C_TFR);
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priv->cli.buffer++;
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priv->cli.count--;
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priv->cli.xfer_bytes++;
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}
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}
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/**
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* write_i2c() - Write data to I2C client.
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* @dev: private data of I2C Driver
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* @priv: private data of I2C Driver
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* @flags: message flags
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*
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* This function writes data to I2C client
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*/
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static int write_i2c(struct nmk_i2c_dev *dev, u16 flags)
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static int write_i2c(struct nmk_i2c_dev *priv, u16 flags)
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{
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u32 status = 0;
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u32 mcr, irq_mask;
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unsigned long timeout;
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mcr = load_i2c_mcr_reg(dev, flags);
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mcr = load_i2c_mcr_reg(priv, flags);
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writel(mcr, dev->virtbase + I2C_MCR);
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writel(mcr, priv->virtbase + I2C_MCR);
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/* load the current CR value */
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writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
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dev->virtbase + I2C_CR);
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writel(readl(priv->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
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priv->virtbase + I2C_CR);
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/* enable the controller */
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i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
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i2c_set_bit(priv->virtbase + I2C_CR, I2C_CR_PE);
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init_completion(&dev->xfer_complete);
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init_completion(&priv->xfer_complete);
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/* enable interrupts by settings the masks */
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irq_mask = (I2C_IT_TXFOVR | I2C_IT_MAL | I2C_IT_BERR);
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/* Fill the TX FIFO with transmit data */
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fill_tx_fifo(dev, MAX_I2C_FIFO_THRESHOLD);
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fill_tx_fifo(priv, MAX_I2C_FIFO_THRESHOLD);
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if (dev->cli.count != 0)
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if (priv->cli.count != 0)
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irq_mask |= I2C_IT_TXFNE;
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/*
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@ -543,23 +542,23 @@ static int write_i2c(struct nmk_i2c_dev *dev, u16 flags)
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* set the MTDWS bit (Master Transaction Done Without Stop)
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* to start repeated start operation
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*/
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if (dev->stop || !dev->vendor->has_mtdws)
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if (priv->stop || !priv->vendor->has_mtdws)
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irq_mask |= I2C_IT_MTD;
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else
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irq_mask |= I2C_IT_MTDWS;
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||||
irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
|
||||
|
||||
writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
|
||||
dev->virtbase + I2C_IMSCR);
|
||||
writel(readl(priv->virtbase + I2C_IMSCR) | irq_mask,
|
||||
priv->virtbase + I2C_IMSCR);
|
||||
|
||||
timeout = wait_for_completion_timeout(
|
||||
&dev->xfer_complete, dev->adap.timeout);
|
||||
&priv->xfer_complete, priv->adap.timeout);
|
||||
|
||||
if (timeout == 0) {
|
||||
/* Controller timed out */
|
||||
dev_err(&dev->adev->dev, "write to slave 0x%x timed out\n",
|
||||
dev->cli.slave_adr);
|
||||
dev_err(&priv->adev->dev, "write to slave 0x%x timed out\n",
|
||||
priv->cli.slave_adr);
|
||||
status = -ETIMEDOUT;
|
||||
}
|
||||
|
||||
@ -568,28 +567,28 @@ static int write_i2c(struct nmk_i2c_dev *dev, u16 flags)
|
||||
|
||||
/**
|
||||
* nmk_i2c_xfer_one() - transmit a single I2C message
|
||||
* @dev: device with a message encoded into it
|
||||
* @priv: device with a message encoded into it
|
||||
* @flags: message flags
|
||||
*/
|
||||
static int nmk_i2c_xfer_one(struct nmk_i2c_dev *dev, u16 flags)
|
||||
static int nmk_i2c_xfer_one(struct nmk_i2c_dev *priv, u16 flags)
|
||||
{
|
||||
int status;
|
||||
|
||||
if (flags & I2C_M_RD) {
|
||||
/* read operation */
|
||||
dev->cli.operation = I2C_READ;
|
||||
status = read_i2c(dev, flags);
|
||||
priv->cli.operation = I2C_READ;
|
||||
status = read_i2c(priv, flags);
|
||||
} else {
|
||||
/* write operation */
|
||||
dev->cli.operation = I2C_WRITE;
|
||||
status = write_i2c(dev, flags);
|
||||
priv->cli.operation = I2C_WRITE;
|
||||
status = write_i2c(priv, flags);
|
||||
}
|
||||
|
||||
if (status || (dev->result)) {
|
||||
if (status || priv->result) {
|
||||
u32 i2c_sr;
|
||||
u32 cause;
|
||||
|
||||
i2c_sr = readl(dev->virtbase + I2C_SR);
|
||||
i2c_sr = readl(priv->virtbase + I2C_SR);
|
||||
/*
|
||||
* Check if the controller I2C operation status
|
||||
* is set to ABORT(11b).
|
||||
@ -597,15 +596,15 @@ static int nmk_i2c_xfer_one(struct nmk_i2c_dev *dev, u16 flags)
|
||||
if (((i2c_sr >> 2) & 0x3) == 0x3) {
|
||||
/* get the abort cause */
|
||||
cause = (i2c_sr >> 4) & 0x7;
|
||||
dev_err(&dev->adev->dev, "%s\n",
|
||||
dev_err(&priv->adev->dev, "%s\n",
|
||||
cause >= ARRAY_SIZE(abort_causes) ?
|
||||
"unknown reason" :
|
||||
abort_causes[cause]);
|
||||
}
|
||||
|
||||
(void) init_hw(dev);
|
||||
init_hw(priv);
|
||||
|
||||
status = status ? status : dev->result;
|
||||
status = status ? status : priv->result;
|
||||
}
|
||||
|
||||
return status;
|
||||
@ -663,24 +662,24 @@ static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap,
|
||||
{
|
||||
int status = 0;
|
||||
int i;
|
||||
struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap);
|
||||
struct nmk_i2c_dev *priv = i2c_get_adapdata(i2c_adap);
|
||||
int j;
|
||||
|
||||
pm_runtime_get_sync(&dev->adev->dev);
|
||||
pm_runtime_get_sync(&priv->adev->dev);
|
||||
|
||||
/* Attempt three times to send the message queue */
|
||||
for (j = 0; j < 3; j++) {
|
||||
/* setup the i2c controller */
|
||||
setup_i2c_controller(dev);
|
||||
setup_i2c_controller(priv);
|
||||
|
||||
for (i = 0; i < num_msgs; i++) {
|
||||
dev->cli.slave_adr = msgs[i].addr;
|
||||
dev->cli.buffer = msgs[i].buf;
|
||||
dev->cli.count = msgs[i].len;
|
||||
dev->stop = (i < (num_msgs - 1)) ? 0 : 1;
|
||||
dev->result = 0;
|
||||
priv->cli.slave_adr = msgs[i].addr;
|
||||
priv->cli.buffer = msgs[i].buf;
|
||||
priv->cli.count = msgs[i].len;
|
||||
priv->stop = (i < (num_msgs - 1)) ? 0 : 1;
|
||||
priv->result = 0;
|
||||
|
||||
status = nmk_i2c_xfer_one(dev, msgs[i].flags);
|
||||
status = nmk_i2c_xfer_one(priv, msgs[i].flags);
|
||||
if (status != 0)
|
||||
break;
|
||||
}
|
||||
@ -688,7 +687,7 @@ static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap,
|
||||
break;
|
||||
}
|
||||
|
||||
pm_runtime_put_sync(&dev->adev->dev);
|
||||
pm_runtime_put_sync(&priv->adev->dev);
|
||||
|
||||
/* return the no. messages processed */
|
||||
if (status)
|
||||
@ -699,14 +698,14 @@ static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap,
|
||||
|
||||
/**
|
||||
* disable_interrupts() - disable the interrupts
|
||||
* @dev: private data of controller
|
||||
* @priv: private data of controller
|
||||
* @irq: interrupt number
|
||||
*/
|
||||
static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq)
|
||||
static int disable_interrupts(struct nmk_i2c_dev *priv, u32 irq)
|
||||
{
|
||||
irq = IRQ_MASK(irq);
|
||||
writel(readl(dev->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq),
|
||||
dev->virtbase + I2C_IMSCR);
|
||||
writel(readl(priv->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq),
|
||||
priv->virtbase + I2C_IMSCR);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -723,17 +722,18 @@ static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq)
|
||||
*/
|
||||
static irqreturn_t i2c_irq_handler(int irq, void *arg)
|
||||
{
|
||||
struct nmk_i2c_dev *dev = arg;
|
||||
struct nmk_i2c_dev *priv = arg;
|
||||
struct device *dev = &priv->adev->dev;
|
||||
u32 tft, rft;
|
||||
u32 count;
|
||||
u32 misr, src;
|
||||
|
||||
/* load Tx FIFO and Rx FIFO threshold values */
|
||||
tft = readl(dev->virtbase + I2C_TFTR);
|
||||
rft = readl(dev->virtbase + I2C_RFTR);
|
||||
tft = readl(priv->virtbase + I2C_TFTR);
|
||||
rft = readl(priv->virtbase + I2C_RFTR);
|
||||
|
||||
/* read interrupt status register */
|
||||
misr = readl(dev->virtbase + I2C_MISR);
|
||||
misr = readl(priv->virtbase + I2C_MISR);
|
||||
|
||||
src = __ffs(misr);
|
||||
switch ((1 << src)) {
|
||||
@ -741,20 +741,20 @@ static irqreturn_t i2c_irq_handler(int irq, void *arg)
|
||||
/* Transmit FIFO nearly empty interrupt */
|
||||
case I2C_IT_TXFNE:
|
||||
{
|
||||
if (dev->cli.operation == I2C_READ) {
|
||||
if (priv->cli.operation == I2C_READ) {
|
||||
/*
|
||||
* in read operation why do we care for writing?
|
||||
* so disable the Transmit FIFO interrupt
|
||||
*/
|
||||
disable_interrupts(dev, I2C_IT_TXFNE);
|
||||
disable_interrupts(priv, I2C_IT_TXFNE);
|
||||
} else {
|
||||
fill_tx_fifo(dev, (MAX_I2C_FIFO_THRESHOLD - tft));
|
||||
fill_tx_fifo(priv, (MAX_I2C_FIFO_THRESHOLD - tft));
|
||||
/*
|
||||
* if done, close the transfer by disabling the
|
||||
* corresponding TXFNE interrupt
|
||||
*/
|
||||
if (dev->cli.count == 0)
|
||||
disable_interrupts(dev, I2C_IT_TXFNE);
|
||||
if (priv->cli.count == 0)
|
||||
disable_interrupts(priv, I2C_IT_TXFNE);
|
||||
}
|
||||
}
|
||||
break;
|
||||
@ -768,60 +768,59 @@ static irqreturn_t i2c_irq_handler(int irq, void *arg)
|
||||
case I2C_IT_RXFNF:
|
||||
for (count = rft; count > 0; count--) {
|
||||
/* Read the Rx FIFO */
|
||||
*dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
|
||||
dev->cli.buffer++;
|
||||
*priv->cli.buffer = readb(priv->virtbase + I2C_RFR);
|
||||
priv->cli.buffer++;
|
||||
}
|
||||
dev->cli.count -= rft;
|
||||
dev->cli.xfer_bytes += rft;
|
||||
priv->cli.count -= rft;
|
||||
priv->cli.xfer_bytes += rft;
|
||||
break;
|
||||
|
||||
/* Rx FIFO full */
|
||||
case I2C_IT_RXFF:
|
||||
for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) {
|
||||
*dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
|
||||
dev->cli.buffer++;
|
||||
*priv->cli.buffer = readb(priv->virtbase + I2C_RFR);
|
||||
priv->cli.buffer++;
|
||||
}
|
||||
dev->cli.count -= MAX_I2C_FIFO_THRESHOLD;
|
||||
dev->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD;
|
||||
priv->cli.count -= MAX_I2C_FIFO_THRESHOLD;
|
||||
priv->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD;
|
||||
break;
|
||||
|
||||
/* Master Transaction Done with/without stop */
|
||||
case I2C_IT_MTD:
|
||||
case I2C_IT_MTDWS:
|
||||
if (dev->cli.operation == I2C_READ) {
|
||||
while (!(readl(dev->virtbase + I2C_RISR)
|
||||
if (priv->cli.operation == I2C_READ) {
|
||||
while (!(readl(priv->virtbase + I2C_RISR)
|
||||
& I2C_IT_RXFE)) {
|
||||
if (dev->cli.count == 0)
|
||||
if (priv->cli.count == 0)
|
||||
break;
|
||||
*dev->cli.buffer =
|
||||
readb(dev->virtbase + I2C_RFR);
|
||||
dev->cli.buffer++;
|
||||
dev->cli.count--;
|
||||
dev->cli.xfer_bytes++;
|
||||
*priv->cli.buffer =
|
||||
readb(priv->virtbase + I2C_RFR);
|
||||
priv->cli.buffer++;
|
||||
priv->cli.count--;
|
||||
priv->cli.xfer_bytes++;
|
||||
}
|
||||
}
|
||||
|
||||
disable_all_interrupts(dev);
|
||||
clear_all_interrupts(dev);
|
||||
disable_all_interrupts(priv);
|
||||
clear_all_interrupts(priv);
|
||||
|
||||
if (dev->cli.count) {
|
||||
dev->result = -EIO;
|
||||
dev_err(&dev->adev->dev,
|
||||
"%lu bytes still remain to be xfered\n",
|
||||
dev->cli.count);
|
||||
(void) init_hw(dev);
|
||||
if (priv->cli.count) {
|
||||
priv->result = -EIO;
|
||||
dev_err(dev, "%lu bytes still remain to be xfered\n",
|
||||
priv->cli.count);
|
||||
init_hw(priv);
|
||||
}
|
||||
complete(&dev->xfer_complete);
|
||||
complete(&priv->xfer_complete);
|
||||
|
||||
break;
|
||||
|
||||
/* Master Arbitration lost interrupt */
|
||||
case I2C_IT_MAL:
|
||||
dev->result = -EIO;
|
||||
(void) init_hw(dev);
|
||||
priv->result = -EIO;
|
||||
init_hw(priv);
|
||||
|
||||
i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MAL);
|
||||
complete(&dev->xfer_complete);
|
||||
i2c_set_bit(priv->virtbase + I2C_ICR, I2C_IT_MAL);
|
||||
complete(&priv->xfer_complete);
|
||||
|
||||
break;
|
||||
|
||||
@ -831,13 +830,13 @@ static irqreturn_t i2c_irq_handler(int irq, void *arg)
|
||||
* during the transaction.
|
||||
*/
|
||||
case I2C_IT_BERR:
|
||||
dev->result = -EIO;
|
||||
priv->result = -EIO;
|
||||
/* get the status */
|
||||
if (((readl(dev->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT)
|
||||
(void) init_hw(dev);
|
||||
if (((readl(priv->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT)
|
||||
init_hw(priv);
|
||||
|
||||
i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_BERR);
|
||||
complete(&dev->xfer_complete);
|
||||
i2c_set_bit(priv->virtbase + I2C_ICR, I2C_IT_BERR);
|
||||
complete(&priv->xfer_complete);
|
||||
|
||||
break;
|
||||
|
||||
@ -847,11 +846,11 @@ static irqreturn_t i2c_irq_handler(int irq, void *arg)
|
||||
* the Tx FIFO is full.
|
||||
*/
|
||||
case I2C_IT_TXFOVR:
|
||||
dev->result = -EIO;
|
||||
(void) init_hw(dev);
|
||||
priv->result = -EIO;
|
||||
init_hw(priv);
|
||||
|
||||
dev_err(&dev->adev->dev, "Tx Fifo Over run\n");
|
||||
complete(&dev->xfer_complete);
|
||||
dev_err(dev, "Tx Fifo Over run\n");
|
||||
complete(&priv->xfer_complete);
|
||||
|
||||
break;
|
||||
|
||||
@ -863,10 +862,10 @@ static irqreturn_t i2c_irq_handler(int irq, void *arg)
|
||||
case I2C_IT_RFSE:
|
||||
case I2C_IT_WTSR:
|
||||
case I2C_IT_STD:
|
||||
dev_err(&dev->adev->dev, "unhandled Interrupt\n");
|
||||
dev_err(dev, "unhandled Interrupt\n");
|
||||
break;
|
||||
default:
|
||||
dev_err(&dev->adev->dev, "spurious Interrupt..\n");
|
||||
dev_err(dev, "spurious Interrupt..\n");
|
||||
break;
|
||||
}
|
||||
|
||||
@ -893,9 +892,9 @@ static int nmk_i2c_resume_early(struct device *dev)
|
||||
static int nmk_i2c_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct amba_device *adev = to_amba_device(dev);
|
||||
struct nmk_i2c_dev *nmk_i2c = amba_get_drvdata(adev);
|
||||
struct nmk_i2c_dev *priv = amba_get_drvdata(adev);
|
||||
|
||||
clk_disable_unprepare(nmk_i2c->clk);
|
||||
clk_disable_unprepare(priv->clk);
|
||||
pinctrl_pm_select_idle_state(dev);
|
||||
return 0;
|
||||
}
|
||||
@ -903,10 +902,10 @@ static int nmk_i2c_runtime_suspend(struct device *dev)
|
||||
static int nmk_i2c_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct amba_device *adev = to_amba_device(dev);
|
||||
struct nmk_i2c_dev *nmk_i2c = amba_get_drvdata(adev);
|
||||
struct nmk_i2c_dev *priv = amba_get_drvdata(adev);
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_enable(nmk_i2c->clk);
|
||||
ret = clk_prepare_enable(priv->clk);
|
||||
if (ret) {
|
||||
dev_err(dev, "can't prepare_enable clock\n");
|
||||
return ret;
|
||||
@ -914,9 +913,9 @@ static int nmk_i2c_runtime_resume(struct device *dev)
|
||||
|
||||
pinctrl_pm_select_default_state(dev);
|
||||
|
||||
ret = init_hw(nmk_i2c);
|
||||
ret = init_hw(priv);
|
||||
if (ret) {
|
||||
clk_disable_unprepare(nmk_i2c->clk);
|
||||
clk_disable_unprepare(priv->clk);
|
||||
pinctrl_pm_select_idle_state(dev);
|
||||
}
|
||||
|
||||
@ -939,107 +938,108 @@ static const struct i2c_algorithm nmk_i2c_algo = {
|
||||
};
|
||||
|
||||
static void nmk_i2c_of_probe(struct device_node *np,
|
||||
struct nmk_i2c_dev *nmk)
|
||||
struct nmk_i2c_dev *priv)
|
||||
{
|
||||
/* Default to 100 kHz if no frequency is given in the node */
|
||||
if (of_property_read_u32(np, "clock-frequency", &nmk->clk_freq))
|
||||
nmk->clk_freq = I2C_MAX_STANDARD_MODE_FREQ;
|
||||
if (of_property_read_u32(np, "clock-frequency", &priv->clk_freq))
|
||||
priv->clk_freq = I2C_MAX_STANDARD_MODE_FREQ;
|
||||
|
||||
/* This driver only supports 'standard' and 'fast' modes of operation. */
|
||||
if (nmk->clk_freq <= I2C_MAX_STANDARD_MODE_FREQ)
|
||||
nmk->sm = I2C_FREQ_MODE_STANDARD;
|
||||
if (priv->clk_freq <= I2C_MAX_STANDARD_MODE_FREQ)
|
||||
priv->sm = I2C_FREQ_MODE_STANDARD;
|
||||
else
|
||||
nmk->sm = I2C_FREQ_MODE_FAST;
|
||||
nmk->tft = 1; /* Tx FIFO threshold */
|
||||
nmk->rft = 8; /* Rx FIFO threshold */
|
||||
nmk->timeout = 200; /* Slave response timeout(ms) */
|
||||
priv->sm = I2C_FREQ_MODE_FAST;
|
||||
priv->tft = 1; /* Tx FIFO threshold */
|
||||
priv->rft = 8; /* Rx FIFO threshold */
|
||||
priv->timeout = 200; /* Slave response timeout(ms) */
|
||||
}
|
||||
|
||||
static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id)
|
||||
{
|
||||
int ret = 0;
|
||||
struct nmk_i2c_dev *priv;
|
||||
struct device_node *np = adev->dev.of_node;
|
||||
struct nmk_i2c_dev *dev;
|
||||
struct device *dev = &adev->dev;
|
||||
struct i2c_adapter *adap;
|
||||
struct i2c_vendor_data *vendor = id->data;
|
||||
u32 max_fifo_threshold = (vendor->fifodepth / 2) - 1;
|
||||
|
||||
dev = devm_kzalloc(&adev->dev, sizeof(*dev), GFP_KERNEL);
|
||||
if (!dev)
|
||||
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
dev->vendor = vendor;
|
||||
dev->adev = adev;
|
||||
nmk_i2c_of_probe(np, dev);
|
||||
priv->vendor = vendor;
|
||||
priv->adev = adev;
|
||||
nmk_i2c_of_probe(np, priv);
|
||||
|
||||
if (dev->tft > max_fifo_threshold) {
|
||||
dev_warn(&adev->dev, "requested TX FIFO threshold %u, adjusted down to %u\n",
|
||||
dev->tft, max_fifo_threshold);
|
||||
dev->tft = max_fifo_threshold;
|
||||
if (priv->tft > max_fifo_threshold) {
|
||||
dev_warn(dev, "requested TX FIFO threshold %u, adjusted down to %u\n",
|
||||
priv->tft, max_fifo_threshold);
|
||||
priv->tft = max_fifo_threshold;
|
||||
}
|
||||
|
||||
if (dev->rft > max_fifo_threshold) {
|
||||
dev_warn(&adev->dev, "requested RX FIFO threshold %u, adjusted down to %u\n",
|
||||
dev->rft, max_fifo_threshold);
|
||||
dev->rft = max_fifo_threshold;
|
||||
if (priv->rft > max_fifo_threshold) {
|
||||
dev_warn(dev, "requested RX FIFO threshold %u, adjusted down to %u\n",
|
||||
priv->rft, max_fifo_threshold);
|
||||
priv->rft = max_fifo_threshold;
|
||||
}
|
||||
|
||||
amba_set_drvdata(adev, dev);
|
||||
amba_set_drvdata(adev, priv);
|
||||
|
||||
dev->virtbase = devm_ioremap(&adev->dev, adev->res.start,
|
||||
resource_size(&adev->res));
|
||||
if (!dev->virtbase)
|
||||
priv->virtbase = devm_ioremap(dev, adev->res.start,
|
||||
resource_size(&adev->res));
|
||||
if (!priv->virtbase)
|
||||
return -ENOMEM;
|
||||
|
||||
dev->irq = adev->irq[0];
|
||||
ret = devm_request_irq(&adev->dev, dev->irq, i2c_irq_handler, 0,
|
||||
DRIVER_NAME, dev);
|
||||
priv->irq = adev->irq[0];
|
||||
ret = devm_request_irq(dev, priv->irq, i2c_irq_handler, 0,
|
||||
DRIVER_NAME, priv);
|
||||
if (ret)
|
||||
return dev_err_probe(&adev->dev, ret,
|
||||
"cannot claim the irq %d\n", dev->irq);
|
||||
return dev_err_probe(dev, ret,
|
||||
"cannot claim the irq %d\n", priv->irq);
|
||||
|
||||
dev->clk = devm_clk_get_enabled(&adev->dev, NULL);
|
||||
if (IS_ERR(dev->clk))
|
||||
return dev_err_probe(&adev->dev, PTR_ERR(dev->clk),
|
||||
priv->clk = devm_clk_get_enabled(dev, NULL);
|
||||
if (IS_ERR(priv->clk))
|
||||
return dev_err_probe(dev, PTR_ERR(priv->clk),
|
||||
"could enable i2c clock\n");
|
||||
|
||||
init_hw(dev);
|
||||
init_hw(priv);
|
||||
|
||||
adap = &dev->adap;
|
||||
adap = &priv->adap;
|
||||
adap->dev.of_node = np;
|
||||
adap->dev.parent = &adev->dev;
|
||||
adap->dev.parent = dev;
|
||||
adap->owner = THIS_MODULE;
|
||||
adap->class = I2C_CLASS_DEPRECATED;
|
||||
adap->algo = &nmk_i2c_algo;
|
||||
adap->timeout = msecs_to_jiffies(dev->timeout);
|
||||
adap->timeout = msecs_to_jiffies(priv->timeout);
|
||||
snprintf(adap->name, sizeof(adap->name),
|
||||
"Nomadik I2C at %pR", &adev->res);
|
||||
|
||||
i2c_set_adapdata(adap, dev);
|
||||
i2c_set_adapdata(adap, priv);
|
||||
|
||||
dev_info(&adev->dev,
|
||||
dev_info(dev,
|
||||
"initialize %s on virtual base %p\n",
|
||||
adap->name, dev->virtbase);
|
||||
adap->name, priv->virtbase);
|
||||
|
||||
ret = i2c_add_adapter(adap);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pm_runtime_put(&adev->dev);
|
||||
pm_runtime_put(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void nmk_i2c_remove(struct amba_device *adev)
|
||||
{
|
||||
struct nmk_i2c_dev *dev = amba_get_drvdata(adev);
|
||||
struct nmk_i2c_dev *priv = amba_get_drvdata(adev);
|
||||
|
||||
i2c_del_adapter(&dev->adap);
|
||||
flush_i2c_fifo(dev);
|
||||
disable_all_interrupts(dev);
|
||||
clear_all_interrupts(dev);
|
||||
i2c_del_adapter(&priv->adap);
|
||||
flush_i2c_fifo(priv);
|
||||
disable_all_interrupts(priv);
|
||||
clear_all_interrupts(priv);
|
||||
/* disable the controller */
|
||||
i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
|
||||
i2c_clr_bit(priv->virtbase + I2C_CR, I2C_CR_PE);
|
||||
}
|
||||
|
||||
static struct i2c_vendor_data vendor_stn8815 = {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user