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clk: mediatek: mt2712: Move apmixedsys clock driver to its own file
The only clock driver that does not support mtk_clk_simple_probe() is apmixedsys: in preparation for enabling module build of non-critical mt2712 clocks, move this to its own file. While at it, also fix some indentation issues in the PLLs table. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Link: https://lore.kernel.org/r/20230306140543.1813621-9-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
AngeloGioacchino Del Regno
Stephen Boyd
parent
20cace1b9d
commit
ae567c3481
@ -38,7 +38,7 @@ obj-$(CONFIG_COMMON_CLK_MT2701_HIFSYS) += clk-mt2701-hif.o
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obj-$(CONFIG_COMMON_CLK_MT2701_IMGSYS) += clk-mt2701-img.o
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obj-$(CONFIG_COMMON_CLK_MT2701_MMSYS) += clk-mt2701-mm.o
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obj-$(CONFIG_COMMON_CLK_MT2701_VDECSYS) += clk-mt2701-vdec.o
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obj-$(CONFIG_COMMON_CLK_MT2712) += clk-mt2712.o
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obj-$(CONFIG_COMMON_CLK_MT2712) += clk-mt2712-apmixedsys.o clk-mt2712.o
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obj-$(CONFIG_COMMON_CLK_MT2712_BDPSYS) += clk-mt2712-bdp.o
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obj-$(CONFIG_COMMON_CLK_MT2712_IMGSYS) += clk-mt2712-img.o
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obj-$(CONFIG_COMMON_CLK_MT2712_JPGDECSYS) += clk-mt2712-jpgdec.o
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153
drivers/clk/mediatek/clk-mt2712-apmixedsys.c
Normal file
153
drivers/clk/mediatek/clk-mt2712-apmixedsys.c
Normal file
@ -0,0 +1,153 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2017 MediaTek Inc.
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* Weiyi Lu <weiyi.lu@mediatek.com>
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* Copyright (c) 2023 Collabora Ltd.
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* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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*/
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#include <linux/clk.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include "clk-pll.h"
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#include "clk-mtk.h"
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#include <dt-bindings/clock/mt2712-clk.h>
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#define MT2712_PLL_FMAX (3000UL * MHZ)
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#define CON0_MT2712_RST_BAR BIT(24)
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#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
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_pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
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_tuner_en_bit, _pcw_reg, _pcw_shift, \
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_div_table) { \
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.id = _id, \
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.name = _name, \
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.reg = _reg, \
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.pwr_reg = _pwr_reg, \
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.en_mask = _en_mask, \
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.flags = _flags, \
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.rst_bar_mask = CON0_MT2712_RST_BAR, \
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.fmax = MT2712_PLL_FMAX, \
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.pcwbits = _pcwbits, \
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.pd_reg = _pd_reg, \
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.pd_shift = _pd_shift, \
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.tuner_reg = _tuner_reg, \
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.tuner_en_reg = _tuner_en_reg, \
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.tuner_en_bit = _tuner_en_bit, \
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.pcw_reg = _pcw_reg, \
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.pcw_shift = _pcw_shift, \
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.div_table = _div_table, \
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}
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#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
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_pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
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_tuner_en_bit, _pcw_reg, _pcw_shift) \
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PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
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_pcwbits, _pd_reg, _pd_shift, _tuner_reg, \
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_tuner_en_reg, _tuner_en_bit, _pcw_reg, \
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_pcw_shift, NULL)
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static const struct mtk_pll_div_table armca35pll_div_table[] = {
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{ .div = 0, .freq = MT2712_PLL_FMAX },
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{ .div = 1, .freq = 1202500000 },
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{ .div = 2, .freq = 500500000 },
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{ .div = 3, .freq = 315250000 },
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{ .div = 4, .freq = 157625000 },
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{ /* sentinel */ }
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};
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static const struct mtk_pll_div_table armca72pll_div_table[] = {
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{ .div = 0, .freq = MT2712_PLL_FMAX },
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{ .div = 1, .freq = 994500000 },
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{ .div = 2, .freq = 520000000 },
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{ .div = 3, .freq = 315250000 },
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{ .div = 4, .freq = 157625000 },
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{ /* sentinel */ }
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};
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static const struct mtk_pll_div_table mmpll_div_table[] = {
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{ .div = 0, .freq = MT2712_PLL_FMAX },
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{ .div = 1, .freq = 1001000000 },
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{ .div = 2, .freq = 601250000 },
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{ .div = 3, .freq = 250250000 },
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{ .div = 4, .freq = 125125000 },
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{ /* sentinel */ }
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};
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static const struct mtk_pll_data plls[] = {
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PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000100,
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HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0),
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PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000100,
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HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0),
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PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000100,
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0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0),
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PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000100,
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0, 31, 0x0280, 4, 0, 0, 0, 0x0284, 0),
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PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000100,
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0, 31, 0x0330, 4, 0x0338, 0x0014, 0, 0x0334, 0),
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PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000100,
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0, 31, 0x0350, 4, 0x0358, 0x0014, 1, 0x0354, 0),
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PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000100,
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0, 31, 0x0370, 4, 0, 0, 0, 0x0374, 0),
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PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000100,
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0, 31, 0x0390, 4, 0, 0, 0, 0x0394, 0),
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PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000100,
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0, 31, 0x0270, 4, 0, 0, 0, 0x0274, 0),
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PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000100,
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0, 31, 0x0410, 4, 0, 0, 0, 0x0414, 0),
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PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000100,
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0, 31, 0x0290, 4, 0, 0, 0, 0x0294, 0),
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PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000100,
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0, 31, 0x0250, 4, 0, 0, 0, 0x0254, 0, mmpll_div_table),
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PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000100,
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HAVE_RST_BAR, 31, 0x0100, 4, 0, 0, 0, 0x0104, 0, armca35pll_div_table),
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PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000100,
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0, 31, 0x0210, 4, 0, 0, 0, 0x0214, 0, armca72pll_div_table),
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PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000100,
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0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),
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};
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static int clk_mt2712_apmixed_probe(struct platform_device *pdev)
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{
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struct clk_hw_onecell_data *clk_data;
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int r;
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struct device_node *node = pdev->dev.of_node;
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clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
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if (!clk_data)
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return -ENOMEM;
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r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
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if (r)
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goto free_clk_data;
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r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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if (r) {
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dev_err(&pdev->dev, "Cannot register clock provider: %d\n", r);
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goto unregister_plls;
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}
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return 0;
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unregister_plls:
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mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
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free_clk_data:
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mtk_free_clk_data(clk_data);
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return r;
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}
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static const struct of_device_id of_match_clk_mt2712_apmixed[] = {
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{ .compatible = "mediatek,mt2712-apmixedsys" },
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{ /* sentinel */ }
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};
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static struct platform_driver clk_mt2712_apmixed_drv = {
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.probe = clk_mt2712_apmixed_probe,
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.driver = {
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.name = "clk-mt2712-apmixed",
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.of_match_table = of_match_clk_mt2712_apmixed,
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},
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};
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builtin_platform_driver(clk_mt2712_apmixed_drv)
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@ -14,7 +14,6 @@
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#include <linux/slab.h>
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#include "clk-gate.h"
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#include "clk-pll.h"
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#include "clk-mtk.h"
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#include <dt-bindings/clock/mt2712-clk.h>
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@ -971,101 +970,6 @@ static const struct mtk_gate peri_clks[] = {
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GATE_PERI2(CLK_PERI_MSDC30_3_QTR_EN, "per_msdc30_3_q", "mem_sel", 7),
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};
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#define MT2712_PLL_FMAX (3000UL * MHZ)
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#define CON0_MT2712_RST_BAR BIT(24)
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#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
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_pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
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_tuner_en_bit, _pcw_reg, _pcw_shift, \
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_div_table) { \
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.id = _id, \
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.name = _name, \
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.reg = _reg, \
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.pwr_reg = _pwr_reg, \
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.en_mask = _en_mask, \
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.flags = _flags, \
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.rst_bar_mask = CON0_MT2712_RST_BAR, \
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.fmax = MT2712_PLL_FMAX, \
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.pcwbits = _pcwbits, \
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.pd_reg = _pd_reg, \
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.pd_shift = _pd_shift, \
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.tuner_reg = _tuner_reg, \
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.tuner_en_reg = _tuner_en_reg, \
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.tuner_en_bit = _tuner_en_bit, \
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.pcw_reg = _pcw_reg, \
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.pcw_shift = _pcw_shift, \
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.div_table = _div_table, \
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}
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#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
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_pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
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_tuner_en_bit, _pcw_reg, _pcw_shift) \
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PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
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_pcwbits, _pd_reg, _pd_shift, _tuner_reg, \
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_tuner_en_reg, _tuner_en_bit, _pcw_reg, \
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_pcw_shift, NULL)
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static const struct mtk_pll_div_table armca35pll_div_table[] = {
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{ .div = 0, .freq = MT2712_PLL_FMAX },
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{ .div = 1, .freq = 1202500000 },
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{ .div = 2, .freq = 500500000 },
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{ .div = 3, .freq = 315250000 },
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{ .div = 4, .freq = 157625000 },
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{ } /* sentinel */
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};
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static const struct mtk_pll_div_table armca72pll_div_table[] = {
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{ .div = 0, .freq = MT2712_PLL_FMAX },
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{ .div = 1, .freq = 994500000 },
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{ .div = 2, .freq = 520000000 },
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{ .div = 3, .freq = 315250000 },
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{ .div = 4, .freq = 157625000 },
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{ } /* sentinel */
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};
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static const struct mtk_pll_div_table mmpll_div_table[] = {
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{ .div = 0, .freq = MT2712_PLL_FMAX },
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{ .div = 1, .freq = 1001000000 },
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{ .div = 2, .freq = 601250000 },
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{ .div = 3, .freq = 250250000 },
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{ .div = 4, .freq = 125125000 },
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{ } /* sentinel */
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};
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static const struct mtk_pll_data plls[] = {
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PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000100,
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HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0),
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PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000100,
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HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0),
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PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000100,
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0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0),
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PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000100,
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0, 31, 0x0280, 4, 0, 0, 0, 0x0284, 0),
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PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000100,
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0, 31, 0x0330, 4, 0x0338, 0x0014, 0, 0x0334, 0),
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PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000100,
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0, 31, 0x0350, 4, 0x0358, 0x0014, 1, 0x0354, 0),
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PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000100,
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0, 31, 0x0370, 4, 0, 0, 0, 0x0374, 0),
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PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000100,
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0, 31, 0x0390, 4, 0, 0, 0, 0x0394, 0),
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PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000100,
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0, 31, 0x0270, 4, 0, 0, 0, 0x0274, 0),
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PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000100,
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0, 31, 0x0410, 4, 0, 0, 0, 0x0414, 0),
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PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000100,
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0, 31, 0x0290, 4, 0, 0, 0, 0x0294, 0),
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PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000100,
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0, 31, 0x0250, 4, 0, 0, 0, 0x0254, 0, mmpll_div_table),
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PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000100,
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HAVE_RST_BAR, 31, 0x0100, 4, 0, 0, 0, 0x0104, 0, armca35pll_div_table),
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PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000100,
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0, 31, 0x0210, 4, 0, 0, 0, 0x0214, 0, armca72pll_div_table),
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PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000100,
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0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),
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};
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static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
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static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
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@ -1084,35 +988,6 @@ static const struct mtk_clk_rst_desc clk_rst_desc[] = {
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},
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};
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static int clk_mt2712_apmixed_probe(struct platform_device *pdev)
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{
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struct clk_hw_onecell_data *clk_data;
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int r;
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struct device_node *node = pdev->dev.of_node;
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clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
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if (!clk_data)
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return -ENOMEM;
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r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
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if (r)
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goto free_clk_data;
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r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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if (r) {
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dev_err(&pdev->dev, "Cannot register clock provider: %d\n", r);
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goto unregister_plls;
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}
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return 0;
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unregister_plls:
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mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
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free_clk_data:
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mtk_free_clk_data(clk_data);
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return r;
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}
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static const struct mtk_clk_desc topck_desc = {
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.clks = top_clks,
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.num_clks = ARRAY_SIZE(top_clks),
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@ -1133,33 +1008,6 @@ static const struct mtk_clk_desc mcu_desc = {
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.clk_lock = &mt2712_clk_lock,
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};
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static const struct of_device_id of_match_clk_mt2712[] = {
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{
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.compatible = "mediatek,mt2712-apmixedsys",
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.data = clk_mt2712_apmixed_probe,
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}, {
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/* sentinel */
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}
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};
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static int clk_mt2712_probe(struct platform_device *pdev)
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{
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int (*clk_probe)(struct platform_device *);
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int r;
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clk_probe = of_device_get_match_data(&pdev->dev);
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if (!clk_probe)
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return -EINVAL;
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r = clk_probe(pdev);
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if (r != 0)
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dev_err(&pdev->dev,
|
||||
"could not register clock provider: %s: %d\n",
|
||||
pdev->name, r);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static const struct mtk_clk_desc infra_desc = {
|
||||
.clks = infra_clks,
|
||||
.num_clks = ARRAY_SIZE(infra_clks),
|
||||
@ -1189,20 +1037,8 @@ static struct platform_driver clk_mt2712_simple_drv = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_driver clk_mt2712_drv = {
|
||||
.probe = clk_mt2712_probe,
|
||||
.driver = {
|
||||
.name = "clk-mt2712",
|
||||
.of_match_table = of_match_clk_mt2712,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init clk_mt2712_init(void)
|
||||
{
|
||||
int ret = platform_driver_register(&clk_mt2712_drv);
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
return platform_driver_register(&clk_mt2712_simple_drv);
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user