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mt8173:

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- use assinged-clocks and assigned-clock-parents
 - fix compatible for SoC to a72
 - add pmu nodes
 
 mt8183:
 - add sysirq binding
 - add pinctrl dt header file
 
 mt7629:
 - update bindings description fo sysirq, uart and scpsys
 
 mt8516:
 - add binding description for watchdog, timer, uart and sysirq
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Merge tag 'v5.1-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt

mt8173:
- use assinged-clocks and assigned-clock-parents
- fix compatible for SoC to a72
- add pmu nodes

mt8183:
- add sysirq binding
- add pinctrl dt header file

mt7629:
- update bindings description fo sysirq, uart and scpsys

mt8516:
- add binding description for watchdog, timer, uart and sysirq

* tag 'v5.1-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  arm64: dts: mt8173: add pmu nodes for mt8173
  arm64: dts: mt8173: correct cpu type of cpu2 and cpu3 to cortex-a72
  dt-bindings: irq: mtk,sysirq: add support for MT8516
  dt-bindings: serial: mtk-uart: add support for MT8516
  dt-bindings: timer: mtk-timer: add support for MT8516
  dt-bindings: wdog: mtk-wdt: add support for MT851
  dt-bindings: soc: fix a typo for MT7623A
  dt-bindings: mediatek: update bindings for MT7629 SoC
  arm64: dts: mt8183: add pinctrl file
  dt-bindings: mtk-sysirq: Add compatible for Mediatek MT8183
  arm64: dts: Using standard CCF interface to set vcodec clk

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2019-04-28 12:59:22 -07:00
commit ad88400145
7 changed files with 1164 additions and 9 deletions
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7
Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
View File

@ -1,15 +1,18 @@
+Mediatek MT65xx/MT67xx/MT81xx sysirq
MediaTek sysirq
Mediatek SOCs sysirq support controllable irq inverter for each GIC SPI
MediaTek SOCs sysirq support controllable irq inverter for each GIC SPI
interrupt.
Required properties:
- compatible: should be
"mediatek,mt8516-sysirq", "mediatek,mt6577-sysirq": for MT8516
"mediatek,mt8183-sysirq", "mediatek,mt6577-sysirq": for MT8183
"mediatek,mt8173-sysirq", "mediatek,mt6577-sysirq": for MT8173
"mediatek,mt8135-sysirq", "mediatek,mt6577-sysirq": for MT8135
"mediatek,mt8127-sysirq", "mediatek,mt6577-sysirq": for MT8127
"mediatek,mt7622-sysirq", "mediatek,mt6577-sysirq": for MT7622
"mediatek,mt7623-sysirq", "mediatek,mt6577-sysirq": for MT7623
"mediatek,mt7629-sysirq", "mediatek,mt6577-sysirq": for MT7629
"mediatek,mt6795-sysirq", "mediatek,mt6577-sysirq": for MT6795
"mediatek,mt6797-sysirq", "mediatek,mt6577-sysirq": for MT6797
"mediatek,mt6765-sysirq", "mediatek,mt6577-sysirq": for MT6765

4
Documentation/devicetree/bindings/serial/mtk-uart.txt
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@ -1,4 +1,4 @@
* Mediatek Universal Asynchronous Receiver/Transmitter (UART)
* MediaTek Universal Asynchronous Receiver/Transmitter (UART)
Required properties:
- compatible should contain:
@ -13,10 +13,12 @@ Required properties:
* "mediatek,mt6797-uart" for MT6797 compatible UARTS
* "mediatek,mt7622-uart" for MT7622 compatible UARTS
* "mediatek,mt7623-uart" for MT7623 compatible UARTS
* "mediatek,mt7629-uart" for MT7629 compatible UARTS
* "mediatek,mt8127-uart" for MT8127 compatible UARTS
* "mediatek,mt8135-uart" for MT8135 compatible UARTS
* "mediatek,mt8173-uart" for MT8173 compatible UARTS
* "mediatek,mt8183-uart", "mediatek,mt6577-uart" for MT8183 compatible UARTS
* "mediatek,mt8516-uart" for MT8516 compatible UARTS
* "mediatek,mt6577-uart" for MT6577 and all of the above
- reg: The base address of the UART register bank.

5
Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
View File

@ -23,6 +23,7 @@ Required properties:
- "mediatek,mt7622-scpsys"
- "mediatek,mt7623-scpsys", "mediatek,mt2701-scpsys": For MT7623 SoC
- "mediatek,mt7623a-scpsys": For MT7623A SoC
- "mediatek,mt7629-scpsys", "mediatek,mt7622-scpsys": For MT7629 SoC
- "mediatek,mt8173-scpsys"
- #power-domain-cells: Must be 1
- reg: Address range of the SCPSYS unit
@ -33,8 +34,8 @@ Required properties:
Required clocks for MT2701 or MT7623: "mm", "mfg", "ethif"
Required clocks for MT2712: "mm", "mfg", "venc", "jpgdec", "audio", "vdec"
Required clocks for MT6797: "mm", "mfg", "vdec"
Required clocks for MT7622: "hif_sel"
Required clocks for MT7622A: "ethif"
Required clocks for MT7622 or MT7629: "hif_sel"
Required clocks for MT7623A: "ethif"
Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
Optional properties:

1
Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
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@ -17,6 +17,7 @@ Required properties:
* "mediatek,mt8127-timer" for MT8127 compatible timers (GPT)
* "mediatek,mt8135-timer" for MT8135 compatible timers (GPT)
* "mediatek,mt8173-timer" for MT8173 compatible timers (GPT)
* "mediatek,mt8516-timer" for MT8516 compatible timers (GPT)
* "mediatek,mt6577-timer" for MT6577 and all above compatible timers (GPT)
For those SoCs that use SYST

1
Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
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@ -9,6 +9,7 @@ Required properties:
"mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622
"mediatek,mt7623-wdt", "mediatek,mt6589-wdt": for MT7623
"mediatek,mt7629-wdt", "mediatek,mt6589-wdt": for MT7629
"mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
- reg : Specifies base physical address and size of the registers.

35
arch/arm64/boot/dts/mediatek/mt8173.dtsi
View File

@ -178,12 +178,12 @@
cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
compatible = "arm,cortex-a72";
reg = <0x100>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
#cooling-cells = <2>;
clocks = <&infracfg CLK_INFRA_CA57SEL>,
clocks = <&infracfg CLK_INFRA_CA72SEL>,
<&apmixedsys CLK_APMIXED_MAINPLL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster1_opp>;
@ -191,12 +191,12 @@
cpu3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a57";
compatible = "arm,cortex-a72";
reg = <0x101>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
#cooling-cells = <2>;
clocks = <&infracfg CLK_INFRA_CA57SEL>,
clocks = <&infracfg CLK_INFRA_CA72SEL>,
<&apmixedsys CLK_APMIXED_MAINPLL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster1_opp>;
@ -216,6 +216,20 @@
};
};
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
interrupt-affinity = <&cpu0>, <&cpu1>;
};
pmu_a72 {
compatible = "arm,cortex-a72-pmu";
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>;
interrupt-affinity = <&cpu2>, <&cpu3>;
};
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
method = "smc";
@ -1307,6 +1321,15 @@
"vencpll",
"venc_lt_sel",
"vdec_bus_clk_src";
assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
<&topckgen CLK_TOP_CCI400_SEL>,
<&topckgen CLK_TOP_VDEC_SEL>,
<&apmixedsys CLK_APMIXED_VCODECPLL>,
<&apmixedsys CLK_APMIXED_VENCPLL>;
assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
<&topckgen CLK_TOP_UNIVPLL_D2>,
<&topckgen CLK_TOP_VCODECPLL>;
assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
};
larb1: larb@16010000 {
@ -1372,6 +1395,10 @@
"venc_sel",
"venc_lt_sel_src",
"venc_lt_sel";
assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
<&topckgen CLK_TOP_VENC_LT_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>,
<&topckgen CLK_TOP_UNIVPLL1_D2>;
};
vencltsys: clock-controller@19000000 {

1120
arch/arm64/boot/dts/mediatek/mt8183-pinfunc.h Normal file
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