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drm/nouveau/kms/nv50: separate out core surface commit
This commit separates the calculation of EVO state from the commit, in order to make the same code useful for atomic modesetting. The legacy interfaces have been wrapped on top of them. As of this commit, we're no longer bothering to point the core surface at a valid framebuffer. Prior to this, we'd initially point the core channel to the framebuffer passed in a mode_set()/mode_set_base(), and then use the base channel for any page-flip updates, leaving the core channel pointing at stale information. The important thing here is to configure the core surface parameters in such a way that EVO's error checking is satisfied. TL;DR: The situation isn't too much different to before. There may be brief periods of times during modesets where the (garbage) core surface will be showing. This issue will be resolved once support for atomic commits has been implemented and we're able to interlock the updates that involve multiple channels. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
3dbd036b84
commit
ad63361953
@ -25,10 +25,11 @@
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#include <linux/dma-mapping.h>
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#include <drm/drmP.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_plane_helper.h>
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#include <drm/drm_dp_helper.h>
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#include <drm/drm_fb_helper.h>
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#include <drm/drm_plane_helper.h>
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#include <nvif/class.h>
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#include <nvif/cl0002.h>
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@ -90,8 +91,41 @@ struct nv50_head_atom {
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} v;
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} mode;
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struct {
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bool visible;
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u32 handle;
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u64 offset:40;
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u8 format;
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u8 kind:7;
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u8 layout:1;
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u8 block:4;
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u32 pitch:20;
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u16 x;
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u16 y;
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u16 w;
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u16 h;
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} core;
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struct {
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u8 depth;
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u8 cpp;
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u16 x;
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u16 y;
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u16 w;
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u16 h;
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} base;
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union {
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struct {
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bool core:1;
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};
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u8 mask;
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} clr;
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union {
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struct {
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bool core:1;
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bool view:1;
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bool mode:1;
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};
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u16 mask;
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@ -737,6 +771,70 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
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* Head
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*****************************************************************************/
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static void
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nv50_head_core_clr(struct nv50_head *head)
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{
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struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
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u32 *push;
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if ((push = evo_wait(core, 2))) {
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if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
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evo_mthd(push, 0x0874 + head->base.index * 0x400, 1);
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else
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evo_mthd(push, 0x0474 + head->base.index * 0x300, 1);
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evo_data(push, 0x00000000);
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evo_kick(push, core);
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}
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}
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static void
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nv50_head_core_set(struct nv50_head *head, struct nv50_head_atom *asyh)
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{
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struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
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u32 *push;
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if ((push = evo_wait(core, 9))) {
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if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
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evo_mthd(push, 0x0860 + head->base.index * 0x400, 1);
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evo_data(push, asyh->core.offset >> 8);
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evo_mthd(push, 0x0868 + head->base.index * 0x400, 4);
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evo_data(push, (asyh->core.h << 16) | asyh->core.w);
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evo_data(push, asyh->core.layout << 20 |
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(asyh->core.pitch >> 8) << 8 |
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asyh->core.block);
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evo_data(push, asyh->core.kind << 16 |
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asyh->core.format << 8);
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evo_data(push, asyh->core.handle);
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evo_mthd(push, 0x08c0 + head->base.index * 0x400, 1);
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evo_data(push, (asyh->core.y << 16) | asyh->core.x);
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} else
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if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
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evo_mthd(push, 0x0860 + head->base.index * 0x400, 1);
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evo_data(push, asyh->core.offset >> 8);
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evo_mthd(push, 0x0868 + head->base.index * 0x400, 4);
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evo_data(push, (asyh->core.h << 16) | asyh->core.w);
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evo_data(push, asyh->core.layout << 20 |
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(asyh->core.pitch >> 8) << 8 |
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asyh->core.block);
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evo_data(push, asyh->core.format << 8);
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evo_data(push, asyh->core.handle);
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evo_mthd(push, 0x08c0 + head->base.index * 0x400, 1);
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evo_data(push, (asyh->core.y << 16) | asyh->core.x);
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} else {
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evo_mthd(push, 0x0460 + head->base.index * 0x300, 1);
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evo_data(push, asyh->core.offset >> 8);
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evo_mthd(push, 0x0468 + head->base.index * 0x300, 4);
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evo_data(push, (asyh->core.h << 16) | asyh->core.w);
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evo_data(push, asyh->core.layout << 24 |
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(asyh->core.pitch >> 8) << 8 |
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asyh->core.block);
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evo_data(push, asyh->core.format << 8);
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evo_data(push, asyh->core.handle);
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evo_mthd(push, 0x04b0 + head->base.index * 0x300, 1);
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evo_data(push, (asyh->core.y << 16) | asyh->core.x);
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}
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evo_kick(push, core);
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}
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}
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static void
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nv50_head_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
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{
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@ -777,10 +875,18 @@ nv50_head_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
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}
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}
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static void
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nv50_head_flush_clr(struct nv50_head *head, struct nv50_head_atom *asyh, bool y)
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{
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if (asyh->clr.core && (!asyh->set.core || y))
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nv50_head_core_clr(head);
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}
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static void
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nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh)
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{
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if (asyh->set.mode ) nv50_head_mode (head, asyh);
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if (asyh->set.core ) nv50_head_core_set(head, asyh);
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}
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static void
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@ -830,16 +936,58 @@ static int
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nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state)
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{
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struct nouveau_drm *drm = nouveau_drm(crtc->dev);
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struct nv50_disp *disp = nv50_disp(crtc->dev);
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struct nv50_head *head = nv50_head(crtc);
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struct nv50_head_atom *armh = &head->arm;
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struct nv50_head_atom *asyh = nv50_head_atom(state);
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NV_ATOMIC(drm, "%s atomic_check %d\n", crtc->name, asyh->state.active);
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asyh->clr.mask = 0;
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asyh->set.mask = 0;
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if (asyh->state.active) {
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if (asyh->state.mode_changed)
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nv50_head_atomic_check_mode(head, asyh);
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if ((asyh->core.visible = (asyh->base.cpp != 0))) {
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asyh->core.x = asyh->base.x;
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asyh->core.y = asyh->base.y;
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asyh->core.w = asyh->base.w;
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asyh->core.h = asyh->base.h;
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} else
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if ((asyh->core.visible = true)) {
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/*XXX: We need to either find some way of having the
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* primary base layer appear black, while still
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* being able to display the other layers, or we
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* need to allocate a dummy black surface here.
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*/
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asyh->core.x = 0;
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asyh->core.y = 0;
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asyh->core.w = asyh->state.mode.hdisplay;
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asyh->core.h = asyh->state.mode.vdisplay;
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}
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asyh->core.handle = disp->mast.base.vram.handle;
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asyh->core.offset = 0;
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asyh->core.format = 0xcf;
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asyh->core.kind = 0;
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asyh->core.layout = 1;
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asyh->core.block = 0;
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asyh->core.pitch = ALIGN(asyh->core.w, 64) * 4;
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} else {
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asyh->core.visible = false;
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}
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if (!drm_atomic_crtc_needs_modeset(&asyh->state)) {
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if (asyh->core.visible) {
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if (memcmp(&armh->core, &asyh->core, sizeof(asyh->core)))
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asyh->set.core = true;
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} else
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if (armh->core.visible) {
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asyh->clr.core = true;
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}
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} else {
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asyh->clr.core = armh->core.visible;
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asyh->set.core = asyh->core.visible;
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}
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memcpy(armh, asyh, sizeof(*asyh));
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@ -1057,41 +1205,31 @@ nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
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int x, int y, bool update)
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{
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struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb);
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struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
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u32 *push;
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struct nv50_head *head = nv50_head(&nv_crtc->base);
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struct nv50_head_atom *asyh = &head->asy;
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const struct drm_format_info *info;
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push = evo_wait(mast, 16);
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if (push) {
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if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
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evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1);
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evo_data(push, nvfb->nvbo->bo.offset >> 8);
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evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3);
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evo_data(push, (fb->height << 16) | fb->width);
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evo_data(push, nvfb->r_pitch);
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evo_data(push, nvfb->r_format);
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evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1);
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evo_data(push, (y << 16) | x);
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if (nv50_vers(mast) > NV50_DISP_CORE_CHANNEL_DMA) {
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evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
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evo_data(push, nvfb->r_handle);
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}
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} else {
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evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1);
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evo_data(push, nvfb->nvbo->bo.offset >> 8);
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evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4);
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evo_data(push, (fb->height << 16) | fb->width);
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evo_data(push, nvfb->r_pitch);
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evo_data(push, nvfb->r_format);
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evo_data(push, nvfb->r_handle);
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evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1);
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evo_data(push, (y << 16) | x);
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}
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info = drm_format_info(nvfb->base.pixel_format);
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if (!info || !info->depth)
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return -EINVAL;
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if (update) {
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asyh->base.depth = info->depth;
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asyh->base.cpp = info->cpp[0];
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asyh->base.x = x;
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asyh->base.y = y;
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asyh->base.w = nvfb->base.width;
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asyh->base.h = nvfb->base.height;
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nv50_head_atomic_check(&head->base.base, &asyh->state);
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nv50_head_flush_set(head, asyh);
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if (update) {
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struct nv50_mast *core = nv50_mast(nv_crtc->base.dev);
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u32 *push = evo_wait(core, 2);
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if (push) {
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evo_mthd(push, 0x0080, 1);
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evo_data(push, 0x00000000);
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evo_kick(push, core);
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}
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evo_kick(push, mast);
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}
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nv_crtc->fb.handle = nvfb->r_handle;
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@ -1183,28 +1321,28 @@ nv50_crtc_prepare(struct drm_crtc *crtc)
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{
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struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
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struct nv50_mast *mast = nv50_mast(crtc->dev);
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struct nv50_head *head = nv50_head(crtc);
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struct nv50_head_atom *asyh = &head->asy;
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u32 *push;
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nv50_display_flip_stop(crtc);
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asyh->state.active = false;
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nv50_head_atomic_check(&head->base.base, &asyh->state);
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nv50_head_flush_clr(head, asyh, false);
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push = evo_wait(mast, 6);
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if (push) {
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if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
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evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
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evo_data(push, 0x00000000);
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evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
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evo_data(push, 0x40000000);
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} else
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if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
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evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
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evo_data(push, 0x00000000);
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evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
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evo_data(push, 0x40000000);
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evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
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evo_data(push, 0x00000000);
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} else {
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evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
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evo_data(push, 0x00000000);
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evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1);
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evo_data(push, 0x03000000);
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evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
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@ -1227,23 +1365,17 @@ nv50_crtc_commit(struct drm_crtc *crtc)
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push = evo_wait(mast, 32);
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if (push) {
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if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
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evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
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evo_data(push, nv_crtc->fb.handle);
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evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
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evo_data(push, 0xc0000000);
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evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
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} else
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if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
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evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
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evo_data(push, nv_crtc->fb.handle);
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evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
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evo_data(push, 0xc0000000);
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evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
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evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
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evo_data(push, mast->base.vram.handle);
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} else {
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evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
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evo_data(push, nv_crtc->fb.handle);
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evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4);
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evo_data(push, 0x83000000);
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evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
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@ -1251,8 +1383,6 @@ nv50_crtc_commit(struct drm_crtc *crtc)
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evo_data(push, 0x00000000);
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evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
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evo_data(push, mast->base.vram.handle);
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evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1);
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evo_data(push, 0xffffff00);
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}
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evo_kick(push, mast);
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