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perf vendor events intel: Refresh alderlake events
Update the alderlake events from 1.16 to 1.18. Generation was done using https://github.com/intel/perfmon. Notable changes are new events and event descriptions, TMA metrics are updated to version 4.5, TMA info metrics are renamed from their node name to be lower case and prefixed by tma_info_, MetricThreshold expressions are added, smi_cost and transaction metric groups are added replicating existing hard coded metrics in stat-shadow. Signed-off-by: Ian Rogers <irogers@google.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Andrii Nakryiko <andrii@kernel.org> Cc: Athira Rajeev <atrajeev@linux.vnet.ibm.com> Cc: Caleb Biggers <caleb.biggers@intel.com> Cc: Eduard Zingerman <eddyz87@gmail.com> Cc: Florian Fischer <florian.fischer@muhq.space> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@arm.com> Cc: Jing Zhang <renyu.zj@linux.alibaba.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: John Garry <john.g.garry@oracle.com> Cc: Kajol Jain <kjain@linux.ibm.com> Cc: Kan Liang <kan.liang@linux.intel.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Perry Taylor <perry.taylor@intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ravi Bangoria <ravi.bangoria@amd.com> Cc: Sandipan Das <sandipan.das@amd.com> Cc: Sean Christopherson <seanjc@google.com> Cc: Stephane Eranian <eranian@google.com> Cc: Suzuki Poulouse <suzuki.poulose@arm.com> Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-11-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Ian Rogers
Arnaldo Carvalho de Melo
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@ -92,19 +92,19 @@
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "All accesses to L2 cache[This event is alias to L2_RQSTS.REFERENCES]",
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"BriefDescription": "All accesses to L2 cache [This event is alias to L2_RQSTS.REFERENCES]",
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"EventCode": "0x24",
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"EventName": "L2_REQUEST.ALL",
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"PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses.[This event is alias to L2_RQSTS.REFERENCES]",
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"PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.REFERENCES]",
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"SampleAfterValue": "200003",
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"UMask": "0xff",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_RQSTS.MISS]",
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"BriefDescription": "Read requests with true-miss in L2 cache. [This event is alias to L2_RQSTS.MISS]",
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"EventCode": "0x24",
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"EventName": "L2_REQUEST.MISS",
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"PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses.[This event is alias to L2_RQSTS.MISS]",
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"PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.MISS]",
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"SampleAfterValue": "200003",
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"UMask": "0x3f",
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"Unit": "cpu_core"
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@ -198,19 +198,19 @@
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_REQUEST.MISS]",
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"BriefDescription": "Read requests with true-miss in L2 cache. [This event is alias to L2_REQUEST.MISS]",
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"EventCode": "0x24",
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"EventName": "L2_RQSTS.MISS",
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"PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses.[This event is alias to L2_REQUEST.MISS]",
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"PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.MISS]",
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"SampleAfterValue": "200003",
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"UMask": "0x3f",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "All accesses to L2 cache[This event is alias to L2_REQUEST.ALL]",
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"BriefDescription": "All accesses to L2 cache [This event is alias to L2_REQUEST.ALL]",
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"EventCode": "0x24",
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"EventName": "L2_RQSTS.REFERENCES",
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"PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses.[This event is alias to L2_REQUEST.ALL]",
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"PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.ALL]",
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"SampleAfterValue": "200003",
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"UMask": "0xff",
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"Unit": "cpu_core"
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@ -895,7 +895,7 @@
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
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"BriefDescription": "Counts demand data reads that resulted in a snoop hit in another cores caches which forwarded the unmodified data to the requesting core.",
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"EventCode": "0x2A,0x2B",
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"EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
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"MSRIndex": "0x1a6,0x1a7",
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@ -980,6 +980,15 @@
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"UMask": "0x8",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Cycles where at least 1 outstanding demand data read request is pending.",
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"CounterMask": "1",
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"EventCode": "0x20",
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"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
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"SampleAfterValue": "2000003",
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"UMask": "0x1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "For every cycle where the core is waiting on at least 1 outstanding Demand RFO request, increments by 1.",
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"CounterMask": "1",
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@ -999,6 +1008,15 @@
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"UMask": "0x8",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.",
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"EventCode": "0x20",
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"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
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"PublicDescription": "For every cycle, increments by the number of outstanding demand data read requests pending. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
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"SampleAfterValue": "1000003",
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"UMask": "0x1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Number of PREFETCHNTA instructions executed.",
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"EventCode": "0x40",
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@ -85,6 +85,24 @@
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"UMask": "0x20",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.",
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"EventCode": "0xc7",
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"EventName": "FP_ARITH_INST_RETIRED.4_FLOPS",
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"PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
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"SampleAfterValue": "100003",
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"UMask": "0x18",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
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"EventCode": "0xc7",
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"EventName": "FP_ARITH_INST_RETIRED.SCALAR",
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"PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
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"SampleAfterValue": "1000003",
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"UMask": "0x3",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
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"EventCode": "0xc7",
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@ -103,6 +121,15 @@
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"UMask": "0x2",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Number of any Vector retired FP arithmetic instructions",
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"EventCode": "0xc7",
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"EventName": "FP_ARITH_INST_RETIRED.VECTOR",
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"PublicDescription": "Number of any Vector retired FP arithmetic instructions. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
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"SampleAfterValue": "1000003",
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"UMask": "0xfc",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",
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"EventCode": "0xc3",
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@ -8,6 +8,15 @@
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"UMask": "0x1",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Clears due to Unknown Branches.",
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"EventCode": "0x60",
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"EventName": "BACLEARS.ANY",
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"PublicDescription": "Number of times the front-end is resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch which occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
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"SampleAfterValue": "100003",
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"UMask": "0x1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Stalls caused by changing prefix length of the instruction.",
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"EventCode": "0x87",
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@ -278,10 +278,9 @@
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Demand Data Read requests who miss L3 cache",
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"BriefDescription": "Counts demand data read requests that miss the L3 cache.",
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"EventCode": "0x21",
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"EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
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"PublicDescription": "Demand Data Read requests who miss L3 cache.",
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"SampleAfterValue": "100003",
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"UMask": "0x10",
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"Unit": "cpu_core"
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@ -793,13 +793,25 @@
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "INST_RETIRED.REP_ITERATION",
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"BriefDescription": "Iterations of Repeat string retired instructions.",
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"EventCode": "0xc0",
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"EventName": "INST_RETIRED.REP_ITERATION",
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"PublicDescription": "Number of iterations of Repeat (REP) string retired instructions such as MOVS, CMPS, and SCAS. Each has a byte, word, and doubleword version and string instructions can be repeated using a repetition prefix, REP, that allows their architectural execution to be repeated a number of times as specified by the RCX register. Note the number of iterations is implementation-dependent.",
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"SampleAfterValue": "2000003",
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"UMask": "0x8",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Clears speculative count",
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"CounterMask": "1",
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"EdgeDetect": "1",
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"EventCode": "0xad",
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"EventName": "INT_MISC.CLEARS_COUNT",
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"PublicDescription": "Counts the number of speculative clears due to any type of branch misprediction or machine clears",
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"SampleAfterValue": "500009",
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"UMask": "0x1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
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"EventCode": "0xad",
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@ -24,7 +24,7 @@
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"Unit": "ARB"
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},
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{
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"BriefDescription": "Number of coherent read requests sent to memory controller that were issued by any core.",
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"BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_REQ_TRK_REQUEST.DRD",
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"EventCode": "0x81",
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"EventName": "UNC_ARB_DAT_REQUESTS.RD",
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"PerPkg": "1",
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@ -40,7 +40,15 @@
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"Unit": "ARB"
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},
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{
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"BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_DAT_REQUESTS.RD",
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"BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_OCCUPANCY.RD]",
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"EventCode": "0x80",
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"EventName": "UNC_ARB_REQ_TRK_OCCUPANCY.DRD",
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"PerPkg": "1",
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"UMask": "0x2",
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"Unit": "ARB"
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},
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{
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"BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_TRK_REQUESTS.RD]",
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"EventCode": "0x81",
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"EventName": "UNC_ARB_REQ_TRK_REQUEST.DRD",
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"PerPkg": "1",
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@ -55,6 +63,14 @@
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"UMask": "0x1",
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"Unit": "ARB"
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},
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{
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"BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries . Such entry is defined as valid when it is allocated till deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_OCCUPANCY.DRD]",
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"EventCode": "0x80",
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"EventName": "UNC_ARB_TRK_OCCUPANCY.RD",
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"PerPkg": "1",
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"UMask": "0x2",
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"Unit": "ARB"
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},
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{
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"BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC.",
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"EventCode": "0x81",
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@ -63,6 +79,14 @@
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"UMask": "0x1",
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"Unit": "ARB"
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},
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{
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"BriefDescription": "Number of all coherent Data Read entries. Doesn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_REQUEST.DRD]",
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"EventCode": "0x81",
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"EventName": "UNC_ARB_TRK_REQUESTS.RD",
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"PerPkg": "1",
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"UMask": "0x2",
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"Unit": "ARB"
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},
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{
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"BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.",
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"EventCode": "0xff",
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@ -1,5 +1,5 @@
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Family-model,Version,Filename,EventType
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GenuineIntel-6-(97|9A|B7|BA|BF),v1.16,alderlake,core
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GenuineIntel-6-(97|9A|B7|BA|BF),v1.18,alderlake,core
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GenuineIntel-6-BE,v1.16,alderlaken,core
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GenuineIntel-6-(1C|26|27|35|36),v4,bonnell,core
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GenuineIntel-6-(3D|47),v26,broadwell,core
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