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- Remove the unconditional cache writeback and invalidation after loading the
microcode patch on Intel as this was addressing a microcode bug for which there is a concrete microcode revision check instead -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEzv7L6UO9uDPlPSfHEsHwGGHeVUoFAmc7Vv4ACgkQEsHwGGHe VUpZtA//erQJlwD+GLWfVoao76Y24LPUVAd20CjvtExDqvOsmvA7lYID89tFXxx0 dD3NDQBW8MI0oZ+Upc9fdRLMWE7SEOQDqk4WlMDMckc1+lv54+lqVA5wv6ee7goY ksUoMQ30MAMZ8ka4vGyjLFsLiYFhVgNCivuJdyi2igABHCGQFSRyl8zog6gWtUTU 3YzTjYjNBY1nZAL99Ibda6VpnmWLOyP24X8hqMp8DD/qqHwhKZfnnqTdoIAkalOq OBK/7vQVaWj5YyUwH/VoJ2iorTv0/XtrNsBRkrxmQaS996/WR8yN4mHbuvThiATc i7b9IEVuoc6KhEuy4sPqt4Yl3QomEed+85/p1NJ5jD6cF4x2+GSnpJF6v/bNRR7T j46jStvJ7f15OcugExRGFI9DjC64ZbHumSrumhLWmKmAqjfAqlYChWUOicHi8l3+ fshTnTRBSUmglGqbkgEVPIRv9e4BkuMpnFCDqAiq8mUm0dzqOZyvvh/gfHTUA+h0 2HykwBitgHEC/e4EHiPpT/Bnm93uL/qBNOhgOWCmOfLGJgdcAE93qP48urj1cbES D5wbNqM5iUvA8jw4frWl222nf7r0FuHVD05pkhJ3m2uvJINWCC3EHFD2Bs3vTEr9 xSGN+nOuWFR2D65RvsMr0eO9x1OTYo679TSyfeTHChnNMWRBcXQ= =wDsa -----END PGP SIGNATURE----- Merge tag 'x86_microcode_for_v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 microcode loader update from Borislav Petkov: - Remove the unconditional cache writeback and invalidation after loading the microcode patch on Intel as this was addressing a microcode bug for which there is a concrete microcode revision check instead * tag 'x86_microcode_for_v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/microcode/intel: Remove unnecessary cache writeback and invalidation
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commit
ab713e7099
@ -319,12 +319,6 @@ static enum ucode_state __apply_microcode(struct ucode_cpu_info *uci,
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return UCODE_OK;
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}
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/*
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* Writeback and invalidate caches before updating microcode to avoid
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* internal issues depending on what the microcode is updating.
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*/
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native_wbinvd();
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/* write microcode via MSR 0x79 */
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native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
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@ -574,14 +568,14 @@ static bool is_blacklisted(unsigned int cpu)
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/*
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* Late loading on model 79 with microcode revision less than 0x0b000021
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* and LLC size per core bigger than 2.5MB may result in a system hang.
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* This behavior is documented in item BDF90, #334165 (Intel Xeon
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* This behavior is documented in item BDX90, #334165 (Intel Xeon
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* Processor E7-8800/4800 v4 Product Family).
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*/
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if (c->x86_vfm == INTEL_BROADWELL_X &&
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c->x86_stepping == 0x01 &&
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llc_size_per_core > 2621440 &&
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c->microcode < 0x0b000021) {
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pr_err_once("Erratum BDF90: late loading with revision < 0x0b000021 (0x%x) disabled.\n", c->microcode);
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pr_err_once("Erratum BDX90: late loading with revision < 0x0b000021 (0x%x) disabled.\n", c->microcode);
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pr_err_once("Please consider either early loading through initrd/built-in or a potential BIOS update.\n");
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return true;
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}
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