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EDAC, AMD: decode instruction cache MCEs

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See Fam10h BKDG (31116, rev. 3.28), Table 95

Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
This commit is contained in:
Borislav Petkov 2009-07-28 14:06:26 +02:00
parent 5196624136
commit ab5535e70f
1 changed files with 61 additions and 0 deletions
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61
drivers/edac/edac_mce_amd.c
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@ -171,6 +171,63 @@ wrong_dc_mce:
pr_warning("Corrupted DC MCE info?\n");
}
static void amd_decode_ic_mce(u64 mc1_status)
{
u32 ec = mc1_status & 0xffff;
u32 xec = (mc1_status >> 16) & 0xf;
pr_emerg(" Instruction Cache Error");
if (xec == 1 && TLB_ERROR(ec))
pr_cont(": %s TLB multimatch.\n", LL_MSG(ec));
else if (xec == 0) {
if (TLB_ERROR(ec))
pr_cont(": %s TLB Parity error.\n", LL_MSG(ec));
else if (BUS_ERROR(ec)) {
if (boot_cpu_data.x86 == 0xf &&
(mc1_status & (1ULL << 58)))
pr_cont(" during system linefill.\n");
else
pr_cont(" during attempted NB data read.\n");
} else if (MEM_ERROR(ec)) {
u8 ll = ec & 0x3;
u8 rrrr = (ec >> 4) & 0xf;
if (ll == 0x2)
pr_cont(" during a linefill from L2.\n");
else if (ll == 0x1) {
switch (rrrr) {
case 0x5:
pr_cont(": Parity error during "
"data load.\n");
break;
case 0x7:
pr_cont(": Copyback Parity/Victim"
" error.\n");
break;
case 0x8:
pr_cont(": Tag Snoop error.\n");
break;
default:
goto wrong_ic_mce;
break;
}
}
} else
goto wrong_ic_mce;
} else
goto wrong_ic_mce;
return;
wrong_ic_mce:
pr_warning("Corrupted IC MCE info?\n");
}
void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors)
{
u32 ec = ERROR_CODE(regs->nbsl);
@ -259,6 +316,10 @@ void decode_mce(struct mce *m)
amd_decode_dc_mce(m->status);
break;
case 1:
amd_decode_ic_mce(m->status);
break;
case 4:
regs.nbsl = (u32) m->status;
regs.nbsh = (u32)(m->status >> 32);