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scsi: ufs: mcq: Add definition for REG_UFS_MEM_CFG register
Instead of hardcoding the register field, add the proper definition. While at it, let's also use ufshcd_rmwl() to simplify updating this register. Reviewed-by: Peter Wang <peter.wang@mediatek.com> Signed-off-by: ChanWoo Lee <cw9316.lee@samsung.com> Link: https://lore.kernel.org/r/20240102014222.23351-1-cw9316.lee@samsung.com Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Bart Van Assche <bvanassche@acm.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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@ -399,6 +399,12 @@ void ufshcd_mcq_enable_esi(struct ufs_hba *hba)
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}
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EXPORT_SYMBOL_GPL(ufshcd_mcq_enable_esi);
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void ufshcd_mcq_enable(struct ufs_hba *hba)
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{
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ufshcd_rmwl(hba, MCQ_MODE_SELECT, MCQ_MODE_SELECT, REG_UFS_MEM_CFG);
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}
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EXPORT_SYMBOL_GPL(ufshcd_mcq_enable);
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void ufshcd_mcq_config_esi(struct ufs_hba *hba, struct msi_msg *msg)
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{
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ufshcd_writel(hba, msg->address_lo, REG_UFS_ESILBA);
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@ -8847,9 +8847,7 @@ static void ufshcd_config_mcq(struct ufs_hba *hba)
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hba->host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED;
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hba->reserved_slot = hba->nutrs - UFSHCD_NUM_RESERVED;
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/* Select MCQ mode */
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ufshcd_writel(hba, ufshcd_readl(hba, REG_UFS_MEM_CFG) | 0x1,
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REG_UFS_MEM_CFG);
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ufshcd_mcq_enable(hba);
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hba->mcq_enabled = true;
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dev_info(hba->dev, "MCQ configured, nr_queues=%d, io_queues=%d, read_queue=%d, poll_queues=%d, queue_depth=%d\n",
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@ -1254,9 +1254,7 @@ static int ufs_mtk_link_set_hpm(struct ufs_hba *hba)
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ufs_mtk_config_mcq(hba, false);
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ufshcd_mcq_make_queues_operational(hba);
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ufshcd_mcq_config_mac(hba, hba->nutrs);
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/* Enable MCQ mode */
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ufshcd_writel(hba, ufshcd_readl(hba, REG_UFS_MEM_CFG) | 0x1,
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REG_UFS_MEM_CFG);
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ufshcd_mcq_enable(hba);
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}
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return 0;
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@ -1267,6 +1267,7 @@ unsigned long ufshcd_mcq_poll_cqe_lock(struct ufs_hba *hba,
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struct ufs_hw_queue *hwq);
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void ufshcd_mcq_make_queues_operational(struct ufs_hba *hba);
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void ufshcd_mcq_enable_esi(struct ufs_hba *hba);
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void ufshcd_mcq_enable(struct ufs_hba *hba);
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void ufshcd_mcq_config_esi(struct ufs_hba *hba, struct msi_msg *msg);
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int ufshcd_opp_config_clks(struct device *dev, struct opp_table *opp_table,
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@ -282,6 +282,9 @@ enum {
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/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
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#define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1
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/* REG_UFS_MEM_CFG - Global Config Registers 300h */
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#define MCQ_MODE_SELECT BIT(0)
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/* CQISy - CQ y Interrupt Status Register */
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#define UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS 0x1
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