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mmc: sdhci-cadence: Support mmc hardware reset
Add support for mmc hardware reset using a reset-controller that would need to be enabled in the device tree with a supporting driver. The default is disabled for all existing designs. Signed-off-by: Brad Larson <blarson@amd.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20230410184526.15990-15-blarson@amd.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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@ -12,6 +12,7 @@
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#include <linux/mmc/mmc.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/reset.h>
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#include "sdhci-pltfm.h"
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@ -70,6 +71,7 @@ struct sdhci_cdns_priv {
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spinlock_t wrlock; /* write lock */
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bool enhanced_strobe;
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void (*priv_writel)(struct sdhci_cdns_priv *priv, u32 val, void __iomem *reg);
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struct reset_control *rst_hw;
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unsigned int nr_phy_params;
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struct sdhci_cdns_phy_param phy_params[];
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};
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@ -457,6 +459,22 @@ static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc,
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SDHCI_CDNS_HRS06_MODE_MMC_HS400);
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}
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static void sdhci_cdns_mmc_hw_reset(struct mmc_host *mmc)
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{
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struct sdhci_host *host = mmc_priv(mmc);
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struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
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dev_dbg(mmc_dev(host->mmc), "emmc hardware reset\n");
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reset_control_assert(priv->rst_hw);
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/* For eMMC, minimum is 1us but give it 3us for good measure */
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udelay(3);
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reset_control_deassert(priv->rst_hw);
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/* For eMMC, minimum is 200us but give it 300us for good measure */
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usleep_range(300, 1000);
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}
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static int sdhci_cdns_probe(struct platform_device *pdev)
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{
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struct sdhci_host *host;
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@ -520,6 +538,15 @@ static int sdhci_cdns_probe(struct platform_device *pdev)
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if (ret)
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goto free;
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if (host->mmc->caps & MMC_CAP_HW_RESET) {
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priv->rst_hw = devm_reset_control_get_optional_exclusive(dev, NULL);
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if (IS_ERR(priv->rst_hw))
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return dev_err_probe(mmc_dev(host->mmc), PTR_ERR(priv->rst_hw),
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"reset controller error\n");
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if (priv->rst_hw)
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host->mmc_host_ops.card_hw_reset = sdhci_cdns_mmc_hw_reset;
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}
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ret = sdhci_add_host(host);
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if (ret)
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goto free;
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