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- Stack size increased to 16K (similar to other 64-bit architectures)
- Additional cache flushing for secondary CPUs boot mode -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) iQIcBAABAgAGBQJR8ojRAAoJEGvWsS0AyF7xoGgP/0kwWr3ND/bsqa6EgF7pVV4K sYU4DgRC2FHlOI0DlW+aRege4ee3NAL9i4GbPV9zOHAEj+Cas4Ytv9MszzhXtdvs I73bigpCsqLIQp68KaLPqjf/WODPBcuK4vZboKF+yTXXe7rq0tBpaSL003ydUxD5 WPgeL92A442hRjgqU3JBm8SERVMaXFYZLY6JwxAmztRliGb+cs3Uh9rSsgiCU9ze eOrRTr8dsR9qY4Iio1vwcl6Id5JSkcZ+WiLs+xdoe10jVfAIvgeJLTizLn1T6eve nVyuhyUR84aElpWtaGpaD2Q5BvFxqt9kun/QgyfGtBShGMN1K3v8avejXY5FXTjT FCq9qU4FzhSp5BAHOUYdgfZcZdU8i68y9HPSIoSvDrttQpHDJNH5kB5vfhKl2PGX POz0KmzTMh1jL4g/LVqmPrGwsKJBpmh/ERifdpwchoKr6UnPVgWG/qbUiQxT4xeY tm5ZxnfWfkpSPcpqWfMdJhv4QU5jeJg5jcigWKF+4Z0uLIXu4h7nPvGjcSN+iYVh zuLEag2aQrxPxYL2OeGjUc1dJ44IacLFjIwRcGmMbj8WXaSGpCoq8PHbGIdt3LEb m7Yo1xAZ85GgR4oqVisAiBma4ZEoE6Gn6o9/crzY8mrS7bV1gv4CGacAfTLH6EyQ cOo0lUnBYOnxEg6ZUpbr =+VTd -----END PGP SIGNATURE----- Merge tag 'arm64-stable' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64 Pull arm64 fixes from Catalin Marinas: - Stack size increased to 16K (similar to other 64-bit architectures) - Additional cache flushing for secondary CPUs boot mode * tag 'arm64-stable' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64: arm64: Change kernel stack size to 16K arm64: Fix definition of arm_pm_restart to match the declaration arm64: virt: ensure visibility of __boot_cpu_mode
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commit
a9b5f02394
@ -24,10 +24,10 @@
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#include <linux/compiler.h>
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#ifndef CONFIG_ARM64_64K_PAGES
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#define THREAD_SIZE_ORDER 1
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#define THREAD_SIZE_ORDER 2
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#endif
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#define THREAD_SIZE 8192
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#define THREAD_SIZE 16384
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#define THREAD_START_SP (THREAD_SIZE - 16)
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#ifndef __ASSEMBLY__
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@ -21,6 +21,7 @@
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#define BOOT_CPU_MODE_EL2 (0x0e12b007)
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#ifndef __ASSEMBLY__
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#include <asm/cacheflush.h>
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/*
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* __boot_cpu_mode records what mode CPUs were booted in.
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@ -36,9 +37,20 @@ extern u32 __boot_cpu_mode[2];
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void __hyp_set_vectors(phys_addr_t phys_vector_base);
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phys_addr_t __hyp_get_vectors(void);
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static inline void sync_boot_mode(void)
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{
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/*
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* As secondaries write to __boot_cpu_mode with caches disabled, we
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* must flush the corresponding cache entries to ensure the visibility
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* of their writes.
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*/
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__flush_dcache_area(__boot_cpu_mode, sizeof(__boot_cpu_mode));
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}
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/* Reports the availability of HYP mode */
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static inline bool is_hyp_mode_available(void)
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{
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sync_boot_mode();
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return (__boot_cpu_mode[0] == BOOT_CPU_MODE_EL2 &&
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__boot_cpu_mode[1] == BOOT_CPU_MODE_EL2);
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}
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@ -46,6 +58,7 @@ static inline bool is_hyp_mode_available(void)
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/* Check if the bootloader has booted CPUs in different modes */
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static inline bool is_hyp_mode_mismatched(void)
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{
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sync_boot_mode();
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return __boot_cpu_mode[0] != __boot_cpu_mode[1];
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}
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@ -121,7 +121,7 @@
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.macro get_thread_info, rd
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mov \rd, sp
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and \rd, \rd, #~((1 << 13) - 1) // top of 8K stack
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and \rd, \rd, #~(THREAD_SIZE - 1) // top of stack
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.endm
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/*
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@ -81,7 +81,7 @@ void soft_restart(unsigned long addr)
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void (*pm_power_off)(void);
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EXPORT_SYMBOL_GPL(pm_power_off);
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void (*arm_pm_restart)(char str, const char *cmd);
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void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
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EXPORT_SYMBOL_GPL(arm_pm_restart);
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void arch_cpu_idle_prepare(void)
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