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KVM: x86 emulator: split dst decode to a generic decode_operand()
Instead of decoding each operand using its own code, use a generic function. Start with the destination operand. Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
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Avi Kivity
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f09ed83e21
commit
a99455499a
@ -28,6 +28,22 @@
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#include "x86.h"
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#include "tss.h"
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/*
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* Operand types
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*/
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#define OpNone 0
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#define OpImplicit 1 /* No generic decode */
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#define OpReg 2 /* Register */
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#define OpMem 3 /* Memory */
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#define OpAcc 4 /* Accumulator: AL/AX/EAX/RAX */
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#define OpDI 5 /* ES:DI/EDI/RDI */
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#define OpMem64 6 /* Memory, 64-bit */
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#define OpImmUByte 7 /* Zero-extended 8-bit immediate */
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#define OpDX 8 /* DX register */
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#define OpBits 4 /* Width of operand field */
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#define OpMask ((1 << OpBits) - 1)
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/*
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* Opcode effective-address decode tables.
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* Note that we only emulate instructions that have at least one memory
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@ -40,15 +56,16 @@
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/* Operand sizes: 8-bit operands or specified/overridden size. */
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#define ByteOp (1<<0) /* 8-bit operands. */
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/* Destination operand type. */
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#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
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#define DstReg (2<<1) /* Register operand. */
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#define DstMem (3<<1) /* Memory operand. */
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#define DstAcc (4<<1) /* Destination Accumulator */
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#define DstDI (5<<1) /* Destination is in ES:(E)DI */
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#define DstMem64 (6<<1) /* 64bit memory operand */
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#define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */
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#define DstDX (8<<1) /* Destination is in DX register */
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#define DstMask (0xf<<1)
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#define DstShift 1
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#define ImplicitOps (OpImplicit << DstShift)
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#define DstReg (OpReg << DstShift)
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#define DstMem (OpMem << DstShift)
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#define DstAcc (OpAcc << DstShift)
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#define DstDI (OpDI << DstShift)
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#define DstMem64 (OpMem64 << DstShift)
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#define DstImmUByte (OpImmUByte << DstShift)
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#define DstDX (OpDX << DstShift)
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#define DstMask (OpMask << DstShift)
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/* Source operand type. */
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#define SrcNone (0<<5) /* No source operand. */
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#define SrcReg (1<<5) /* Register operand. */
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@ -3316,6 +3333,66 @@ done:
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return rc;
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}
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static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
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unsigned d)
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{
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int rc = X86EMUL_CONTINUE;
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switch (d) {
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case OpReg:
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decode_register_operand(ctxt, op,
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ctxt->twobyte && (ctxt->b == 0xb6 || ctxt->b == 0xb7));
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break;
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case OpImmUByte:
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op->type = OP_IMM;
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op->addr.mem.ea = ctxt->_eip;
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op->bytes = 1;
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op->val = insn_fetch(u8, ctxt);
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break;
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case OpMem:
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case OpMem64:
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*op = ctxt->memop;
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ctxt->memopp = op;
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if (d == OpMem64)
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op->bytes = 8;
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else
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op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
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if (ctxt->d & BitOp)
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fetch_bit_operand(ctxt);
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op->orig_val = op->val;
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break;
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case OpAcc:
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op->type = OP_REG;
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op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
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op->addr.reg = &ctxt->regs[VCPU_REGS_RAX];
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fetch_register_operand(op);
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op->orig_val = op->val;
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break;
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case OpDI:
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op->type = OP_MEM;
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op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
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op->addr.mem.ea =
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register_address(ctxt, ctxt->regs[VCPU_REGS_RDI]);
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op->addr.mem.seg = VCPU_SREG_ES;
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op->val = 0;
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break;
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case OpDX:
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op->type = OP_REG;
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op->bytes = 2;
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op->addr.reg = &ctxt->regs[VCPU_REGS_RDX];
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fetch_register_operand(op);
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break;
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case OpImplicit:
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/* Special instructions do their own operand decoding. */
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default:
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op->type = OP_NONE; /* Disable writeback. */
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break;
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}
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done:
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return rc;
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}
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int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
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{
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int rc = X86EMUL_CONTINUE;
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@ -3602,56 +3679,7 @@ done_prefixes:
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goto done;
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/* Decode and fetch the destination operand: register or memory. */
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switch (ctxt->d & DstMask) {
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case DstReg:
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decode_register_operand(ctxt, &ctxt->dst,
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ctxt->twobyte && (ctxt->b == 0xb6 || ctxt->b == 0xb7));
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break;
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case DstImmUByte:
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ctxt->dst.type = OP_IMM;
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ctxt->dst.addr.mem.ea = ctxt->_eip;
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ctxt->dst.bytes = 1;
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ctxt->dst.val = insn_fetch(u8, ctxt);
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break;
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case DstMem:
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case DstMem64:
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ctxt->dst = ctxt->memop;
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ctxt->memopp = &ctxt->dst;
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if ((ctxt->d & DstMask) == DstMem64)
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ctxt->dst.bytes = 8;
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else
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ctxt->dst.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
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if (ctxt->d & BitOp)
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fetch_bit_operand(ctxt);
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ctxt->dst.orig_val = ctxt->dst.val;
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break;
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case DstAcc:
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ctxt->dst.type = OP_REG;
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ctxt->dst.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
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ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RAX];
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fetch_register_operand(&ctxt->dst);
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ctxt->dst.orig_val = ctxt->dst.val;
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break;
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case DstDI:
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ctxt->dst.type = OP_MEM;
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ctxt->dst.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
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ctxt->dst.addr.mem.ea =
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register_address(ctxt, ctxt->regs[VCPU_REGS_RDI]);
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ctxt->dst.addr.mem.seg = VCPU_SREG_ES;
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ctxt->dst.val = 0;
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break;
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case DstDX:
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ctxt->dst.type = OP_REG;
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ctxt->dst.bytes = 2;
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ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RDX];
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fetch_register_operand(&ctxt->dst);
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break;
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case ImplicitOps:
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/* Special instructions do their own operand decoding. */
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default:
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ctxt->dst.type = OP_NONE; /* Disable writeback. */
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break;
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}
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rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
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done:
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if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
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