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qlcnic: Fix endian issues in 83xx driver
o Split mailbox structure elements on boundary of adapter register size i.e. 32bit. o Shuffle the position of structure elements based on CPU endianness. Signed-off-by: Shahed Shaikh <shahed.shaikh@qlogic.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Shahed Shaikh
David S. Miller
parent
23bdbc80e1
commit
a96227e66f
@ -15,36 +15,57 @@
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#define RSS_HASHTYPE_IP_TCP 0x3
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/* status descriptor mailbox data
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* @phy_addr: physical address of buffer
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* @phy_addr_{low|high}: physical address of buffer
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* @sds_ring_size: buffer size
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* @intrpt_id: interrupt id
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* @intrpt_val: source of interrupt
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*/
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struct qlcnic_sds_mbx {
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u64 phy_addr;
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u8 rsvd1[16];
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u32 phy_addr_low;
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u32 phy_addr_high;
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u32 rsvd1[4];
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#if defined(__LITTLE_ENDIAN)
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u16 sds_ring_size;
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u16 rsvd2[3];
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u16 rsvd2;
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u16 rsvd3[2];
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u16 intrpt_id;
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u8 intrpt_val;
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u8 rsvd3[5];
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u8 rsvd4;
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#elif defined(__BIG_ENDIAN)
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u16 rsvd2;
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u16 sds_ring_size;
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u16 rsvd3[2];
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u8 rsvd4;
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u8 intrpt_val;
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u16 intrpt_id;
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#endif
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u32 rsvd5;
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} __packed;
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/* receive descriptor buffer data
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* phy_addr_reg: physical address of regular buffer
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* phy_addr_jmb: physical address of jumbo buffer
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* phy_addr_reg_{low|high}: physical address of regular buffer
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* phy_addr_jmb_{low|high}: physical address of jumbo buffer
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* reg_ring_sz: size of regular buffer
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* reg_ring_len: no. of entries in regular buffer
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* jmb_ring_len: no. of entries in jumbo buffer
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* jmb_ring_sz: size of jumbo buffer
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*/
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struct qlcnic_rds_mbx {
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u64 phy_addr_reg;
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u64 phy_addr_jmb;
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u32 phy_addr_reg_low;
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u32 phy_addr_reg_high;
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u32 phy_addr_jmb_low;
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u32 phy_addr_jmb_high;
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#if defined(__LITTLE_ENDIAN)
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u16 reg_ring_sz;
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u16 reg_ring_len;
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u16 jmb_ring_sz;
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u16 jmb_ring_len;
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#elif defined(__BIG_ENDIAN)
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u16 reg_ring_len;
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u16 reg_ring_sz;
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u16 jmb_ring_len;
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u16 jmb_ring_sz;
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#endif
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} __packed;
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/* host producers for regular and jumbo rings */
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@ -61,6 +82,7 @@ struct __host_producer_mbx {
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* @phy_port: physical port id
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*/
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struct qlcnic_rcv_mbx_out {
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#if defined(__LITTLE_ENDIAN)
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u8 rcv_num;
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u8 sts_num;
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u16 ctx_id;
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@ -68,32 +90,56 @@ struct qlcnic_rcv_mbx_out {
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u8 num_pci_func;
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u8 phy_port;
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u8 vport_id;
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#elif defined(__BIG_ENDIAN)
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u16 ctx_id;
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u8 sts_num;
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u8 rcv_num;
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u8 vport_id;
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u8 phy_port;
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u8 num_pci_func;
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u8 state;
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#endif
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u32 host_csmr[QLCNIC_MAX_RING_SETS];
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struct __host_producer_mbx host_prod[QLCNIC_MAX_RING_SETS];
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} __packed;
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struct qlcnic_add_rings_mbx_out {
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#if defined(__LITTLE_ENDIAN)
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u8 rcv_num;
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u8 sts_num;
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u16 ctx_id;
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u16 ctx_id;
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#elif defined(__BIG_ENDIAN)
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u16 ctx_id;
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u8 sts_num;
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u8 rcv_num;
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#endif
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u32 host_csmr[QLCNIC_MAX_RING_SETS];
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struct __host_producer_mbx host_prod[QLCNIC_MAX_RING_SETS];
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} __packed;
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/* Transmit context mailbox inbox registers
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* @phys_addr: DMA address of the transmit buffer
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* @cnsmr_index: host consumer index
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* @phys_addr_{low|high}: DMA address of the transmit buffer
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* @cnsmr_index_{low|high}: host consumer index
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* @size: legth of transmit buffer ring
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* @intr_id: interrput id
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* @src: src of interrupt
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*/
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struct qlcnic_tx_mbx {
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u64 phys_addr;
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u64 cnsmr_index;
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u32 phys_addr_low;
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u32 phys_addr_high;
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u32 cnsmr_index_low;
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u32 cnsmr_index_high;
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#if defined(__LITTLE_ENDIAN)
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u16 size;
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u16 intr_id;
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u8 src;
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u8 rsvd[3];
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#elif defined(__BIG_ENDIAN)
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u16 intr_id;
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u16 size;
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u8 rsvd[3];
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u8 src;
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#endif
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} __packed;
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/* Transmit context mailbox outbox registers
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@ -101,11 +147,18 @@ struct qlcnic_tx_mbx {
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* @ctx_id: transmit context id
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* @state: state of the transmit context
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*/
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struct qlcnic_tx_mbx_out {
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u32 host_prod;
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#if defined(__LITTLE_ENDIAN)
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u16 ctx_id;
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u8 state;
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u8 rsvd;
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#elif defined(__BIG_ENDIAN)
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u8 rsvd;
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u8 state;
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u16 ctx_id;
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#endif
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} __packed;
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static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl[] = {
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@ -1004,7 +1057,8 @@ static int qlcnic_83xx_add_rings(struct qlcnic_adapter *adapter)
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sds = &recv_ctx->sds_rings[i];
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sds->consumer = 0;
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memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
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sds_mbx.phy_addr = sds->phys_addr;
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sds_mbx.phy_addr_low = LSD(sds->phys_addr);
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sds_mbx.phy_addr_high = MSD(sds->phys_addr);
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sds_mbx.sds_ring_size = sds->num_desc;
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if (adapter->flags & QLCNIC_MSIX_ENABLED)
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@ -1090,7 +1144,8 @@ int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *adapter)
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sds = &recv_ctx->sds_rings[i];
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sds->consumer = 0;
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memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
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sds_mbx.phy_addr = sds->phys_addr;
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sds_mbx.phy_addr_low = LSD(sds->phys_addr);
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sds_mbx.phy_addr_high = MSD(sds->phys_addr);
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sds_mbx.sds_ring_size = sds->num_desc;
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if (adapter->flags & QLCNIC_MSIX_ENABLED)
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intrpt_id = ahw->intr_tbl[i].id;
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@ -1110,13 +1165,15 @@ int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *adapter)
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rds = &recv_ctx->rds_rings[0];
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rds->producer = 0;
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memset(&rds_mbx, 0, rds_mbx_size);
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rds_mbx.phy_addr_reg = rds->phys_addr;
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rds_mbx.phy_addr_reg_low = LSD(rds->phys_addr);
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rds_mbx.phy_addr_reg_high = MSD(rds->phys_addr);
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rds_mbx.reg_ring_sz = rds->dma_size;
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rds_mbx.reg_ring_len = rds->num_desc;
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/* Jumbo ring */
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rds = &recv_ctx->rds_rings[1];
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rds->producer = 0;
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rds_mbx.phy_addr_jmb = rds->phys_addr;
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rds_mbx.phy_addr_jmb_low = LSD(rds->phys_addr);
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rds_mbx.phy_addr_jmb_high = MSD(rds->phys_addr);
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rds_mbx.jmb_ring_sz = rds->dma_size;
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rds_mbx.jmb_ring_len = rds->num_desc;
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buf = &cmd.req.arg[index];
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@ -1182,8 +1239,10 @@ int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *adapter,
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memset(&mbx, 0, sizeof(struct qlcnic_tx_mbx));
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/* setup mailbox inbox registerss */
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mbx.phys_addr = tx->phys_addr;
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mbx.cnsmr_index = tx->hw_cons_phys_addr;
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mbx.phys_addr_low = LSD(tx->phys_addr);
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mbx.phys_addr_high = MSD(tx->phys_addr);
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mbx.cnsmr_index_low = LSD(tx->hw_cons_phys_addr);
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mbx.cnsmr_index_high = MSD(tx->hw_cons_phys_addr);
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mbx.size = tx->num_desc;
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if (adapter->flags & QLCNIC_MSIX_ENABLED)
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msix_id = ahw->intr_tbl[adapter->max_sds_rings + ring].id;
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@ -1713,7 +1772,12 @@ int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
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(adapter->recv_ctx->context_id << 16);
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mv.vlan = le16_to_cpu(vlan_id);
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memcpy(&mv.mac, addr, ETH_ALEN);
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mv.mac_addr0 = addr[0];
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mv.mac_addr1 = addr[1];
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mv.mac_addr2 = addr[2];
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mv.mac_addr3 = addr[3];
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mv.mac_addr4 = addr[4];
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mv.mac_addr5 = addr[5];
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buf = &cmd.req.arg[2];
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memcpy(buf, &mv, sizeof(struct qlcnic_macvlan_mbx));
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err = qlcnic_issue_cmd(adapter, &cmd);
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@ -94,8 +94,23 @@ struct qlcnic_intrpt_config {
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};
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struct qlcnic_macvlan_mbx {
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u8 mac[ETH_ALEN];
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#if defined(__LITTLE_ENDIAN)
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u8 mac_addr0;
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u8 mac_addr1;
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u8 mac_addr2;
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u8 mac_addr3;
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u8 mac_addr4;
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u8 mac_addr5;
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u16 vlan;
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#elif defined(__BIG_ENDIAN)
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u8 mac_addr3;
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u8 mac_addr2;
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u8 mac_addr1;
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u8 mac_addr0;
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u16 vlan;
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u8 mac_addr5;
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u8 mac_addr4;
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#endif
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};
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struct qlc_83xx_fw_info {
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@ -31,6 +31,7 @@ static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter);
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/* Template header */
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struct qlc_83xx_reset_hdr {
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#if defined(__LITTLE_ENDIAN)
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u16 version;
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u16 signature;
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u16 size;
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@ -39,14 +40,31 @@ struct qlc_83xx_reset_hdr {
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u16 checksum;
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u16 init_offset;
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u16 start_offset;
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#elif defined(__BIG_ENDIAN)
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u16 signature;
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u16 version;
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u16 entries;
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u16 size;
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u16 checksum;
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u16 hdr_size;
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u16 start_offset;
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u16 init_offset;
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#endif
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} __packed;
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/* Command entry header. */
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struct qlc_83xx_entry_hdr {
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u16 cmd;
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u16 size;
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u16 count;
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u16 delay;
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#if defined(__LITTLE_ENDIAN)
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u16 cmd;
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u16 size;
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u16 count;
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u16 delay;
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#elif defined(__BIG_ENDIAN)
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u16 size;
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u16 cmd;
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u16 delay;
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u16 count;
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#endif
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} __packed;
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/* Generic poll command */
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@ -60,10 +78,17 @@ struct qlc_83xx_rmw {
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u32 mask;
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u32 xor_value;
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u32 or_value;
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#if defined(__LITTLE_ENDIAN)
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u8 shl;
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u8 shr;
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u8 index_a;
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u8 rsvd;
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#elif defined(__BIG_ENDIAN)
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u8 rsvd;
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u8 index_a;
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u8 shr;
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u8 shl;
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#endif
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} __packed;
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/* Generic command with 2 DWORD */
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