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soc: mediatek: mtk-svs: Use bitfield access macros where possible
In order to enhance readability and safety during registers setup and value retrieval, redefine a few register related macros and convert all open-coded instances of bitfield setting/retrieval to use the FIELD_PREP() and FIELD_GET() macros. While at it, some macros were renamed to further enhance readability. This commit brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20220825184616.2118870-3-nfraprado@collabora.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
AngeloGioacchino Del Regno
Matthias Brugger
parent
43819e3853
commit
a92438c5a3
@ -53,22 +53,79 @@
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#define SVSB_MON_VOLT_IGNORE BIT(16)
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#define SVSB_REMOVE_DVTFIXED_VOLT BIT(24)
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/* svs bank register common configuration */
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#define SVSB_DET_MAX 0xffff
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/* svs bank register fields and common configuration */
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#define SVSB_PTPCONFIG_DETMAX GENMASK(15, 0)
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#define SVSB_DET_MAX FIELD_PREP(SVSB_PTPCONFIG_DETMAX, 0xffff)
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#define SVSB_DET_WINDOW 0xa28
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#define SVSB_DTHI 0x1
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#define SVSB_DTLO 0xfe
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#define SVSB_EN_INIT01 0x1
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#define SVSB_EN_INIT02 0x5
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#define SVSB_EN_MON 0x2
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#define SVSB_EN_OFF 0x0
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#define SVSB_INTEN_INIT0x 0x00005f01
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#define SVSB_INTEN_MONVOPEN 0x00ff0000
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#define SVSB_INTSTS_CLEAN 0x00ffffff
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#define SVSB_INTSTS_COMPLETE 0x1
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#define SVSB_INTSTS_MONVOP 0x00ff0000
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/* DESCHAR */
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#define SVSB_DESCHAR_FLD_MDES GENMASK(7, 0)
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#define SVSB_DESCHAR_FLD_BDES GENMASK(15, 8)
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/* TEMPCHAR */
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#define SVSB_TEMPCHAR_FLD_DVT_FIXED GENMASK(7, 0)
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#define SVSB_TEMPCHAR_FLD_MTDES GENMASK(15, 8)
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#define SVSB_TEMPCHAR_FLD_VCO GENMASK(23, 16)
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/* DETCHAR */
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#define SVSB_DETCHAR_FLD_DCMDET GENMASK(7, 0)
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#define SVSB_DETCHAR_FLD_DCBDET GENMASK(15, 8)
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/* SVSEN (PTPEN) */
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#define SVSB_PTPEN_INIT01 BIT(0)
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#define SVSB_PTPEN_MON BIT(1)
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#define SVSB_PTPEN_INIT02 (SVSB_PTPEN_INIT01 | BIT(2))
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#define SVSB_PTPEN_OFF 0x0
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/* FREQPCTS */
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#define SVSB_FREQPCTS_FLD_PCT0_4 GENMASK(7, 0)
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#define SVSB_FREQPCTS_FLD_PCT1_5 GENMASK(15, 8)
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#define SVSB_FREQPCTS_FLD_PCT2_6 GENMASK(23, 16)
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#define SVSB_FREQPCTS_FLD_PCT3_7 GENMASK(31, 24)
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/* INTSTS */
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#define SVSB_INTSTS_VAL_CLEAN 0x00ffffff
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#define SVSB_INTSTS_F0_COMPLETE BIT(0)
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#define SVSB_INTSTS_FLD_MONVOP GENMASK(23, 16)
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#define SVSB_RUNCONFIG_DEFAULT 0x80000000
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/* LIMITVALS */
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#define SVSB_LIMITVALS_FLD_DTLO GENMASK(7, 0)
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#define SVSB_LIMITVALS_FLD_DTHI GENMASK(15, 8)
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#define SVSB_LIMITVALS_FLD_VMIN GENMASK(23, 16)
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#define SVSB_LIMITVALS_FLD_VMAX GENMASK(31, 24)
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#define SVSB_VAL_DTHI 0x1
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#define SVSB_VAL_DTLO 0xfe
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/* INTEN */
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#define SVSB_INTEN_F0EN BIT(0)
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#define SVSB_INTEN_DACK0UPEN BIT(8)
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#define SVSB_INTEN_DC0EN BIT(9)
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#define SVSB_INTEN_DC1EN BIT(10)
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#define SVSB_INTEN_DACK0LOEN BIT(11)
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#define SVSB_INTEN_INITPROD_OVF_EN BIT(12)
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#define SVSB_INTEN_INITSUM_OVF_EN BIT(14)
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#define SVSB_INTEN_MONVOPEN GENMASK(23, 16)
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#define SVSB_INTEN_INIT0x (SVSB_INTEN_F0EN | SVSB_INTEN_DACK0UPEN | \
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SVSB_INTEN_DC0EN | SVSB_INTEN_DC1EN | \
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SVSB_INTEN_DACK0LOEN | \
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SVSB_INTEN_INITPROD_OVF_EN | \
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SVSB_INTEN_INITSUM_OVF_EN)
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/* TSCALCS */
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#define SVSB_TSCALCS_FLD_MTS GENMASK(11, 0)
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#define SVSB_TSCALCS_FLD_BTS GENMASK(23, 12)
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/* INIT2VALS */
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#define SVSB_INIT2VALS_FLD_DCVOFFSETIN GENMASK(15, 0)
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#define SVSB_INIT2VALS_FLD_AGEVOFFSETIN GENMASK(31, 16)
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/* VOPS */
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#define SVSB_VOPS_FLD_VOP0_4 GENMASK(7, 0)
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#define SVSB_VOPS_FLD_VOP1_5 GENMASK(15, 8)
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#define SVSB_VOPS_FLD_VOP2_6 GENMASK(23, 16)
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#define SVSB_VOPS_FLD_VOP3_7 GENMASK(31, 24)
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/* svs bank related setting */
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#define BITS8 8
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#define MAX_OPP_ENTRIES 16
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@ -665,8 +722,8 @@ static ssize_t svs_enable_debug_write(struct file *filp,
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svsp->pbank = svsb;
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svsb->mode_support = SVSB_MODE_ALL_DISABLE;
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svs_switch_bank(svsp);
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svs_writel_relaxed(svsp, SVSB_EN_OFF, SVSEN);
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svs_writel_relaxed(svsp, SVSB_INTSTS_CLEAN, INTSTS);
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svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN);
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svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS);
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spin_unlock_irqrestore(&svs_lock, flags);
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svsb->phase = SVSB_PHASE_ERROR;
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@ -827,7 +884,7 @@ static void svs_get_bank_volts_v3(struct svs_platform *svsp)
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} else if (svsb->type == SVSB_LOW) {
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/* volt[turn_pt] + volt[j] ~ volt[opp_count - 1] */
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j = svsb->opp_count - 7;
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svsb->volt[turn_pt] = vop30 & GENMASK(7, 0);
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svsb->volt[turn_pt] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30);
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shift_byte++;
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for (i = j; i < svsb->opp_count; i++) {
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b_sft = BITS8 * (shift_byte % REG_BYTES);
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@ -849,7 +906,7 @@ static void svs_get_bank_volts_v3(struct svs_platform *svsp)
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if (svsb->type == SVSB_HIGH) {
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/* volt[0] + volt[j] ~ volt[turn_pt - 1] */
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j = turn_pt - 7;
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svsb->volt[0] = vop30 & GENMASK(7, 0);
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svsb->volt[0] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30);
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shift_byte++;
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for (i = j; i < turn_pt; i++) {
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b_sft = BITS8 * (shift_byte % REG_BYTES);
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@ -980,16 +1037,16 @@ static void svs_get_bank_volts_v2(struct svs_platform *svsp)
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u32 temp, i;
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temp = svs_readl_relaxed(svsp, VOP74);
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svsb->volt[14] = (temp >> 24) & GENMASK(7, 0);
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svsb->volt[12] = (temp >> 16) & GENMASK(7, 0);
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svsb->volt[10] = (temp >> 8) & GENMASK(7, 0);
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svsb->volt[8] = (temp & GENMASK(7, 0));
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svsb->volt[14] = FIELD_GET(SVSB_VOPS_FLD_VOP3_7, temp);
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svsb->volt[12] = FIELD_GET(SVSB_VOPS_FLD_VOP2_6, temp);
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svsb->volt[10] = FIELD_GET(SVSB_VOPS_FLD_VOP1_5, temp);
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svsb->volt[8] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, temp);
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temp = svs_readl_relaxed(svsp, VOP30);
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svsb->volt[6] = (temp >> 24) & GENMASK(7, 0);
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svsb->volt[4] = (temp >> 16) & GENMASK(7, 0);
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svsb->volt[2] = (temp >> 8) & GENMASK(7, 0);
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svsb->volt[0] = (temp & GENMASK(7, 0));
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svsb->volt[6] = FIELD_GET(SVSB_VOPS_FLD_VOP3_7, temp);
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svsb->volt[4] = FIELD_GET(SVSB_VOPS_FLD_VOP2_6, temp);
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svsb->volt[2] = FIELD_GET(SVSB_VOPS_FLD_VOP1_5, temp);
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svsb->volt[0] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, temp);
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for (i = 0; i <= 12; i += 2)
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svsb->volt[i + 1] = interpolate(svsb->freq_pct[i],
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@ -1011,20 +1068,20 @@ static void svs_get_bank_volts_v2(struct svs_platform *svsp)
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static void svs_set_bank_freq_pct_v2(struct svs_platform *svsp)
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{
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struct svs_bank *svsb = svsp->pbank;
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u32 freqpct74_val, freqpct30_val;
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svs_writel_relaxed(svsp,
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(svsb->freq_pct[14] << 24) |
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(svsb->freq_pct[12] << 16) |
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(svsb->freq_pct[10] << 8) |
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svsb->freq_pct[8],
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FREQPCT74);
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freqpct74_val = FIELD_PREP(SVSB_FREQPCTS_FLD_PCT0_4, svsb->freq_pct[8]) |
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FIELD_PREP(SVSB_FREQPCTS_FLD_PCT1_5, svsb->freq_pct[10]) |
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FIELD_PREP(SVSB_FREQPCTS_FLD_PCT2_6, svsb->freq_pct[12]) |
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FIELD_PREP(SVSB_FREQPCTS_FLD_PCT3_7, svsb->freq_pct[14]);
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svs_writel_relaxed(svsp,
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(svsb->freq_pct[6] << 24) |
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(svsb->freq_pct[4] << 16) |
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(svsb->freq_pct[2] << 8) |
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svsb->freq_pct[0],
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FREQPCT30);
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freqpct30_val = FIELD_PREP(SVSB_FREQPCTS_FLD_PCT0_4, svsb->freq_pct[0]) |
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FIELD_PREP(SVSB_FREQPCTS_FLD_PCT1_5, svsb->freq_pct[2]) |
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FIELD_PREP(SVSB_FREQPCTS_FLD_PCT2_6, svsb->freq_pct[4]) |
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FIELD_PREP(SVSB_FREQPCTS_FLD_PCT3_7, svsb->freq_pct[6]);
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svs_writel_relaxed(svsp, freqpct74_val, FREQPCT74);
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svs_writel_relaxed(svsp, freqpct30_val, FREQPCT30);
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}
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static void svs_set_bank_phase(struct svs_platform *svsp,
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@ -1035,13 +1092,17 @@ static void svs_set_bank_phase(struct svs_platform *svsp,
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svs_switch_bank(svsp);
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des_char = (svsb->bdes << 8) | svsb->mdes;
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des_char = FIELD_PREP(SVSB_DESCHAR_FLD_BDES, svsb->bdes) |
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FIELD_PREP(SVSB_DESCHAR_FLD_MDES, svsb->mdes);
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svs_writel_relaxed(svsp, des_char, DESCHAR);
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temp_char = (svsb->vco << 16) | (svsb->mtdes << 8) | svsb->dvt_fixed;
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temp_char = FIELD_PREP(SVSB_TEMPCHAR_FLD_VCO, svsb->vco) |
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FIELD_PREP(SVSB_TEMPCHAR_FLD_MTDES, svsb->mtdes) |
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FIELD_PREP(SVSB_TEMPCHAR_FLD_DVT_FIXED, svsb->dvt_fixed);
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svs_writel_relaxed(svsp, temp_char, TEMPCHAR);
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det_char = (svsb->dcbdet << 8) | svsb->dcmdet;
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det_char = FIELD_PREP(SVSB_DETCHAR_FLD_DCBDET, svsb->dcbdet) |
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FIELD_PREP(SVSB_DETCHAR_FLD_DCMDET, svsb->dcmdet);
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svs_writel_relaxed(svsp, det_char, DETCHAR);
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svs_writel_relaxed(svsp, svsb->dc_config, DCCONFIG);
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@ -1050,33 +1111,37 @@ static void svs_set_bank_phase(struct svs_platform *svsp,
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svsb->set_freq_pct(svsp);
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limit_vals = (svsb->vmax << 24) | (svsb->vmin << 16) |
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(SVSB_DTHI << 8) | SVSB_DTLO;
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limit_vals = FIELD_PREP(SVSB_LIMITVALS_FLD_DTLO, SVSB_VAL_DTLO) |
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FIELD_PREP(SVSB_LIMITVALS_FLD_DTHI, SVSB_VAL_DTHI) |
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FIELD_PREP(SVSB_LIMITVALS_FLD_VMIN, svsb->vmin) |
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FIELD_PREP(SVSB_LIMITVALS_FLD_VMAX, svsb->vmax);
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svs_writel_relaxed(svsp, limit_vals, LIMITVALS);
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svs_writel_relaxed(svsp, SVSB_DET_WINDOW, DETWINDOW);
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svs_writel_relaxed(svsp, SVSB_DET_MAX, CONFIG);
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svs_writel_relaxed(svsp, svsb->chk_shift, CHKSHIFT);
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svs_writel_relaxed(svsp, svsb->ctl0, CTL0);
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svs_writel_relaxed(svsp, SVSB_INTSTS_CLEAN, INTSTS);
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svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS);
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switch (target_phase) {
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case SVSB_PHASE_INIT01:
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svs_writel_relaxed(svsp, svsb->vboot, VBOOT);
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svs_writel_relaxed(svsp, SVSB_INTEN_INIT0x, INTEN);
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svs_writel_relaxed(svsp, SVSB_EN_INIT01, SVSEN);
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svs_writel_relaxed(svsp, SVSB_PTPEN_INIT01, SVSEN);
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break;
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case SVSB_PHASE_INIT02:
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init2vals = FIELD_PREP(SVSB_INIT2VALS_FLD_AGEVOFFSETIN, svsb->age_voffset_in) |
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FIELD_PREP(SVSB_INIT2VALS_FLD_DCVOFFSETIN, svsb->dc_voffset_in);
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svs_writel_relaxed(svsp, SVSB_INTEN_INIT0x, INTEN);
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init2vals = (svsb->age_voffset_in << 16) | svsb->dc_voffset_in;
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svs_writel_relaxed(svsp, init2vals, INIT2VALS);
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svs_writel_relaxed(svsp, SVSB_EN_INIT02, SVSEN);
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svs_writel_relaxed(svsp, SVSB_PTPEN_INIT02, SVSEN);
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break;
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case SVSB_PHASE_MON:
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ts_calcs = (svsb->bts << 12) | svsb->mts;
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ts_calcs = FIELD_PREP(SVSB_TSCALCS_FLD_BTS, svsb->bts) |
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FIELD_PREP(SVSB_TSCALCS_FLD_MTS, svsb->mts);
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svs_writel_relaxed(svsp, ts_calcs, TSCALCS);
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svs_writel_relaxed(svsp, SVSB_INTEN_MONVOPEN, INTEN);
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svs_writel_relaxed(svsp, SVSB_EN_MON, SVSEN);
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svs_writel_relaxed(svsp, SVSB_PTPEN_MON, SVSEN);
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break;
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default:
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dev_err(svsb->dev, "requested unknown target phase: %u\n",
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@ -1112,8 +1177,8 @@ static inline void svs_error_isr_handler(struct svs_platform *svsp)
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svs_save_bank_register_data(svsp, SVSB_PHASE_ERROR);
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svsb->phase = SVSB_PHASE_ERROR;
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svs_writel_relaxed(svsp, SVSB_EN_OFF, SVSEN);
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svs_writel_relaxed(svsp, SVSB_INTSTS_CLEAN, INTSTS);
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svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN);
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svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS);
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}
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static inline void svs_init01_isr_handler(struct svs_platform *svsp)
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@ -1138,8 +1203,8 @@ static inline void svs_init01_isr_handler(struct svs_platform *svsp)
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svsb->age_voffset_in = svs_readl_relaxed(svsp, AGEVALUES) &
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GENMASK(15, 0);
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svs_writel_relaxed(svsp, SVSB_EN_OFF, SVSEN);
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svs_writel_relaxed(svsp, SVSB_INTSTS_COMPLETE, INTSTS);
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svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN);
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svs_writel_relaxed(svsp, SVSB_INTSTS_F0_COMPLETE, INTSTS);
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svsb->core_sel &= ~SVSB_DET_CLK_EN;
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}
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@ -1157,8 +1222,8 @@ static inline void svs_init02_isr_handler(struct svs_platform *svsp)
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svsb->phase = SVSB_PHASE_INIT02;
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svsb->get_volts(svsp);
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svs_writel_relaxed(svsp, SVSB_EN_OFF, SVSEN);
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svs_writel_relaxed(svsp, SVSB_INTSTS_COMPLETE, INTSTS);
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svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN);
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svs_writel_relaxed(svsp, SVSB_INTSTS_F0_COMPLETE, INTSTS);
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}
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static inline void svs_mon_mode_isr_handler(struct svs_platform *svsp)
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@ -1171,7 +1236,7 @@ static inline void svs_mon_mode_isr_handler(struct svs_platform *svsp)
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svsb->get_volts(svsp);
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svsb->temp = svs_readl_relaxed(svsp, TEMP) & GENMASK(7, 0);
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svs_writel_relaxed(svsp, SVSB_INTSTS_MONVOP, INTSTS);
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svs_writel_relaxed(svsp, SVSB_INTSTS_FLD_MONVOP, INTSTS);
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}
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static irqreturn_t svs_isr(int irq, void *data)
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@ -1198,13 +1263,13 @@ static irqreturn_t svs_isr(int irq, void *data)
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int_sts = svs_readl_relaxed(svsp, INTSTS);
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svs_en = svs_readl_relaxed(svsp, SVSEN);
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if (int_sts == SVSB_INTSTS_COMPLETE &&
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svs_en == SVSB_EN_INIT01)
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if (int_sts == SVSB_INTSTS_F0_COMPLETE &&
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svs_en == SVSB_PTPEN_INIT01)
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svs_init01_isr_handler(svsp);
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else if (int_sts == SVSB_INTSTS_COMPLETE &&
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svs_en == SVSB_EN_INIT02)
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else if (int_sts == SVSB_INTSTS_F0_COMPLETE &&
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svs_en == SVSB_PTPEN_INIT02)
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svs_init02_isr_handler(svsp);
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else if (int_sts & SVSB_INTSTS_MONVOP)
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else if (int_sts & SVSB_INTSTS_FLD_MONVOP)
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svs_mon_mode_isr_handler(svsp);
|
||||
else
|
||||
svs_error_isr_handler(svsp);
|
||||
@ -1490,8 +1555,8 @@ static int svs_suspend(struct device *dev)
|
||||
spin_lock_irqsave(&svs_lock, flags);
|
||||
svsp->pbank = svsb;
|
||||
svs_switch_bank(svsp);
|
||||
svs_writel_relaxed(svsp, SVSB_EN_OFF, SVSEN);
|
||||
svs_writel_relaxed(svsp, SVSB_INTSTS_CLEAN, INTSTS);
|
||||
svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN);
|
||||
svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS);
|
||||
spin_unlock_irqrestore(&svs_lock, flags);
|
||||
|
||||
svsb->phase = SVSB_PHASE_ERROR;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user