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[ARM] 4577/1: ITE 8152 PCI bridge support
This patch provides driver for ITE 8152 PCI bridge. Signed-off-by: Mike Rapoport <mike@compulab.co.il> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Mike Rapoport
Russell King
parent
3696a8a426
commit
a8fc078955
@ -17,3 +17,4 @@ obj-$(CONFIG_SHARPSL_PM) += sharpsl_pm.o
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obj-$(CONFIG_SHARP_SCOOP) += scoop.o
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obj-$(CONFIG_ARCH_IXP2000) += uengine.o
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obj-$(CONFIG_ARCH_IXP23XX) += uengine.o
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obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o
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387
arch/arm/common/it8152.c
Normal file
387
arch/arm/common/it8152.c
Normal file
@ -0,0 +1,387 @@
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/*
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* linux/arch/arm/common/it8152.c
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*
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* Copyright Compulab Ltd, 2002-2007
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* Mike Rapoport <mike@compulab.co.il>
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*
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* The DMA bouncing part is taken from arch/arm/mach-ixp4xx/common-pci.c
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* (see this file for respective copyrights)
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*
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* Thanks to Guennadi Liakhovetski <gl@dsa-ac.de> for IRQ enumberation
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* and demux code.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/ptrace.h>
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#include <linux/interrupt.h>
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#include <linux/mm.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/mach/pci.h>
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#include <asm/hardware/it8152.h>
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#define MAX_SLOTS 21
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static void it8152_mask_irq(unsigned int irq)
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{
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if (irq >= IT8152_LD_IRQ(0)) {
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__raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) |
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(1 << (irq - IT8152_LD_IRQ(0)))),
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IT8152_INTC_LDCNIMR);
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} else if (irq >= IT8152_LP_IRQ(0)) {
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__raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) |
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(1 << (irq - IT8152_LP_IRQ(0)))),
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IT8152_INTC_LPCNIMR);
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} else if (irq >= IT8152_PD_IRQ(0)) {
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__raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) |
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(1 << (irq - IT8152_PD_IRQ(0)))),
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IT8152_INTC_PDCNIMR);
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}
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}
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static void it8152_unmask_irq(unsigned int irq)
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{
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if (irq >= IT8152_LD_IRQ(0)) {
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__raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) &
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~(1 << (irq - IT8152_LD_IRQ(0)))),
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IT8152_INTC_LDCNIMR);
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} else if (irq >= IT8152_LP_IRQ(0)) {
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__raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) &
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~(1 << (irq - IT8152_LP_IRQ(0)))),
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IT8152_INTC_LPCNIMR);
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} else if (irq >= IT8152_PD_IRQ(0)) {
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__raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) &
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~(1 << (irq - IT8152_PD_IRQ(0)))),
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IT8152_INTC_PDCNIMR);
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}
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}
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static inline void it8152_irq(int irq)
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{
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struct irq_desc *desc;
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printk(KERN_DEBUG "===> %s: irq=%d\n", __FUNCTION__, irq);
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desc = irq_desc + irq;
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desc_handle_irq(irq, desc);
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}
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static struct irq_chip it8152_irq_chip = {
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.name = "it8152",
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.ack = it8152_mask_irq,
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.mask = it8152_mask_irq,
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.unmask = it8152_unmask_irq,
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};
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void it8152_init_irq(void)
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{
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int irq;
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__raw_writel((0xffff), IT8152_INTC_PDCNIMR);
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__raw_writel((0), IT8152_INTC_PDCNIRR);
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__raw_writel((0xffff), IT8152_INTC_LPCNIMR);
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__raw_writel((0), IT8152_INTC_LPCNIRR);
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__raw_writel((0xffff), IT8152_INTC_LDCNIMR);
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__raw_writel((0), IT8152_INTC_LDCNIRR);
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for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) {
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set_irq_chip(irq, &it8152_irq_chip);
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set_irq_handler(irq, handle_level_irq);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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}
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}
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void it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
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{
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int bits_pd, bits_lp, bits_ld;
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int i;
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printk(KERN_DEBUG "=> %s: irq = %d\n", __FUNCTION__, irq);
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while (1) {
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/* Read all */
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bits_pd = __raw_readl(IT8152_INTC_PDCNIRR);
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bits_lp = __raw_readl(IT8152_INTC_LPCNIRR);
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bits_ld = __raw_readl(IT8152_INTC_LDCNIRR);
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/* Ack */
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__raw_writel((~bits_pd), IT8152_INTC_PDCNIRR);
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__raw_writel((~bits_lp), IT8152_INTC_LPCNIRR);
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__raw_writel((~bits_ld), IT8152_INTC_LDCNIRR);
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if (!(bits_ld | bits_lp | bits_pd)) {
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/* Re-read to guarantee, that there was a moment of
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time, when they all three were 0. */
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bits_pd = __raw_readl(IT8152_INTC_PDCNIRR);
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bits_lp = __raw_readl(IT8152_INTC_LPCNIRR);
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if (!(bits_ld | bits_lp | bits_pd))
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return;
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}
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bits_pd &= ((1 << IT8152_PD_IRQ_COUNT) - 1);
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while (bits_pd) {
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i = __ffs(bits_pd);
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it8152_irq(IT8152_PD_IRQ(i));
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bits_pd &= ~(1 << i);
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}
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bits_lp &= ((1 << IT8152_LP_IRQ_COUNT) - 1);
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while (bits_lp) {
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i = __ffs(bits_pd);
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it8152_irq(IT8152_LP_IRQ(i));
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bits_lp &= ~(1 << i);
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}
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bits_ld &= ((1 << IT8152_LD_IRQ_COUNT) - 1);
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while (bits_ld) {
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i = __ffs(bits_pd);
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it8152_irq(IT8152_LD_IRQ(i));
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bits_ld &= ~(1 << i);
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}
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}
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}
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/* mapping for on-chip devices */
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int __init it8152_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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if ((dev->vendor == PCI_VENDOR_ID_ITE) &&
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(dev->device == PCI_DEVICE_ID_ITE_8152)) {
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if ((dev->class >> 8) == PCI_CLASS_MULTIMEDIA_AUDIO)
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return IT8152_AUDIO_INT;
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if ((dev->class >> 8) == PCI_CLASS_SERIAL_USB)
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return IT8152_USB_INT;
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if ((dev->class >> 8) == PCI_CLASS_SYSTEM_DMA)
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return IT8152_CDMA_INT;
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}
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return 0;
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}
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static unsigned long it8152_pci_dev_base_address(struct pci_bus *bus,
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unsigned int devfn)
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{
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unsigned long addr = 0;
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if (bus->number == 0) {
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if (devfn < PCI_DEVFN(MAX_SLOTS, 0))
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addr = (devfn << 8);
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} else
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addr = (bus->number << 16) | (devfn << 8);
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return addr;
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}
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static int it8152_pci_read_config(struct pci_bus *bus,
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unsigned int devfn, int where,
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int size, u32 *value)
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{
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unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
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u32 v;
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int shift;
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shift = (where & 3);
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__raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
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v = (__raw_readl(IT8152_PCI_CFG_DATA) >> (8 * (shift)));
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*value = v;
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return PCIBIOS_SUCCESSFUL;
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}
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static int it8152_pci_write_config(struct pci_bus *bus,
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unsigned int devfn, int where,
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int size, u32 value)
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{
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unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
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u32 v, vtemp, mask = 0;
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int shift;
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if (size == 1)
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mask = 0xff;
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if (size == 2)
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mask = 0xffff;
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shift = (where & 3);
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__raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
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vtemp = __raw_readl(IT8152_PCI_CFG_DATA);
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if (mask)
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vtemp &= ~(mask << (8 * shift));
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else
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vtemp = 0;
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v = (value << (8 * shift));
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__raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
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__raw_writel((v | vtemp), IT8152_PCI_CFG_DATA);
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops it8152_ops = {
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.read = it8152_pci_read_config,
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.write = it8152_pci_write_config,
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};
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static struct resource it8152_io = {
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.name = "IT8152 PCI I/O region",
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.flags = IORESOURCE_IO,
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};
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static struct resource it8152_mem = {
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.name = "IT8152 PCI memory region",
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.start = 0x10000000,
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.end = 0x13e00000,
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.flags = IORESOURCE_MEM,
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};
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/*
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* The following functions are needed for DMA bouncing.
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* ITE8152 chip can addrees up to 64MByte, so all the devices
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* connected to ITE8152 (PCI and USB) should have limited DMA window
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*/
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/*
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* Setup DMA mask to 64MB on devices connected to ITE8152. Ignore all
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* other devices.
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*/
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static int it8152_pci_platform_notify(struct device *dev)
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{
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if (dev->bus == &pci_bus_type) {
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if (dev->dma_mask)
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*dev->dma_mask = (SZ_64M - 1) | PHYS_OFFSET;
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dev->coherent_dma_mask = (SZ_64M - 1) | PHYS_OFFSET;
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dmabounce_register_dev(dev, 2048, 4096);
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}
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return 0;
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}
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static int it8152_pci_platform_notify_remove(struct device *dev)
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{
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if (dev->bus == &pci_bus_type)
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dmabounce_unregister_dev(dev);
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return 0;
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}
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int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
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{
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dev_dbg(dev, "%s: dma_addr %08x, size %08x\n",
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__FUNCTION__, dma_addr, size);
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return (dev->bus == &pci_bus_type) &&
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((dma_addr + size - PHYS_OFFSET) >= SZ_64M);
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}
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/*
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* We override these so we properly do dmabounce otherwise drivers
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* are able to set the dma_mask to 0xffffffff and we can no longer
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* trap bounces. :(
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*
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* We just return true on everyhing except for < 64MB in which case
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* we will fail miseralby and die since we can't handle that case.
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*/
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int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
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{
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printk(KERN_DEBUG "%s: %s %llx\n",
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__FUNCTION__, dev->dev.bus_id, mask);
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if (mask >= PHYS_OFFSET + SZ_64M - 1)
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return 0;
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return -EIO;
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}
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int
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pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
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{
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printk(KERN_DEBUG "%s: %s %llx\n",
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__FUNCTION__, dev->dev.bus_id, mask);
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if (mask >= PHYS_OFFSET + SZ_64M - 1)
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return 0;
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return -EIO;
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}
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int __init it8152_pci_setup(int nr, struct pci_sys_data *sys)
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{
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it8152_io.start = IT8152_IO_BASE + 0x12000;
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it8152_io.end = IT8152_IO_BASE + 0x12000 + 0x100000;
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sys->mem_offset = 0x10000000;
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sys->io_offset = IT8152_IO_BASE;
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if (request_resource(&ioport_resource, &it8152_io)) {
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printk(KERN_ERR "PCI: unable to allocate IO region\n");
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goto err0;
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}
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if (request_resource(&iomem_resource, &it8152_mem)) {
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printk(KERN_ERR "PCI: unable to allocate memory region\n");
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goto err1;
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}
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sys->resource[0] = &it8152_io;
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sys->resource[1] = &it8152_mem;
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if (platform_notify || platform_notify_remove) {
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printk(KERN_ERR "PCI: Can't use platform_notify\n");
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goto err2;
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}
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platform_notify = it8152_pci_platform_notify;
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platform_notify_remove = it8152_pci_platform_notify_remove;
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return 1;
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err2:
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release_resource(&it8152_io);
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err1:
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release_resource(&it8152_mem);
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err0:
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return -EBUSY;
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}
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/*
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* If we set up a device for bus mastering, we need to check the latency
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* timer as we don't have even crappy BIOSes to set it properly.
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* The implementation is from arch/i386/pci/i386.c
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*/
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unsigned int pcibios_max_latency = 255;
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void pcibios_set_master(struct pci_dev *dev)
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{
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u8 lat;
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/* no need to update on-chip OHCI controller */
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if ((dev->vendor == PCI_VENDOR_ID_ITE) &&
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(dev->device == PCI_DEVICE_ID_ITE_8152) &&
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((dev->class >> 8) == PCI_CLASS_SERIAL_USB))
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return;
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pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
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if (lat < 16)
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lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
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else if (lat > pcibios_max_latency)
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lat = pcibios_max_latency;
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else
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return;
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printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
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pci_name(dev), lat);
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
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}
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struct pci_bus * __init it8152_pci_scan_bus(int nr, struct pci_sys_data *sys)
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{
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return pci_scan_bus(nr, &it8152_ops, sys);
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}
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@ -279,6 +279,25 @@ static void __devinit pci_fixup_cy82c693(struct pci_dev *dev)
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);
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static void __init pci_fixup_it8152(struct pci_dev *dev)
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{
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int i;
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/* fixup for ITE 8152 devices */
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/* FIXME: add defines for class 0x68000 and 0x80103 */
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if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST ||
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dev->class == 0x68000 ||
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dev->class == 0x80103) {
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for (i = 0; i < PCI_NUM_RESOURCES; i++) {
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dev->resource[i].start = 0;
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dev->resource[i].end = 0;
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dev->resource[i].flags = 0;
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}
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152);
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void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
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{
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if (debug_pci)
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@ -292,9 +311,12 @@ void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
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*/
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static inline int pdev_bad_for_parity(struct pci_dev *dev)
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{
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return (dev->vendor == PCI_VENDOR_ID_INTERG &&
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(dev->device == PCI_DEVICE_ID_INTERG_2000 ||
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dev->device == PCI_DEVICE_ID_INTERG_2010));
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return ((dev->vendor == PCI_VENDOR_ID_INTERG &&
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(dev->device == PCI_DEVICE_ID_INTERG_2000 ||
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dev->device == PCI_DEVICE_ID_INTERG_2010)) ||
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(dev->vendor == PCI_VENDOR_ID_ITE &&
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dev->device == PCI_DEVICE_ID_ITE_8152));
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}
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/*
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99
include/asm-arm/hardware/it8152.h
Normal file
99
include/asm-arm/hardware/it8152.h
Normal file
@ -0,0 +1,99 @@
|
||||
/*
|
||||
* linux/include/arm/hardware/it8152.h
|
||||
*
|
||||
* Copyright Compulab Ltd., 2006,2007
|
||||
* Mike Rapoport <mike@compulab.co.il>
|
||||
*
|
||||
* ITE 8152 companion chip register definitions
|
||||
*/
|
||||
|
||||
#ifndef __ASM_HARDWARE_IT8152_H
|
||||
#define __ASM_HARDWARE_IT8152_H
|
||||
extern unsigned long it8152_base_address;
|
||||
|
||||
#define IT8152_IO_BASE (it8152_base_address + 0x03e00000)
|
||||
#define IT8152_CFGREG_BASE (it8152_base_address + 0x03f00000)
|
||||
|
||||
#define __REG_IT8152(x) (it8152_base_address + (x))
|
||||
|
||||
#define IT8152_PCI_CFG_ADDR __REG_IT8152(0x3f00800)
|
||||
#define IT8152_PCI_CFG_DATA __REG_IT8152(0x3f00804)
|
||||
|
||||
#define IT8152_INTC_LDCNIRR __REG_IT8152(0x3f00300)
|
||||
#define IT8152_INTC_LDPNIRR __REG_IT8152(0x3f00304)
|
||||
#define IT8152_INTC_LDCNIMR __REG_IT8152(0x3f00308)
|
||||
#define IT8152_INTC_LDPNIMR __REG_IT8152(0x3f0030C)
|
||||
#define IT8152_INTC_LDNITR __REG_IT8152(0x3f00310)
|
||||
#define IT8152_INTC_LDNIAR __REG_IT8152(0x3f00314)
|
||||
#define IT8152_INTC_LPCNIRR __REG_IT8152(0x3f00320)
|
||||
#define IT8152_INTC_LPPNIRR __REG_IT8152(0x3f00324)
|
||||
#define IT8152_INTC_LPCNIMR __REG_IT8152(0x3f00328)
|
||||
#define IT8152_INTC_LPPNIMR __REG_IT8152(0x3f0032C)
|
||||
#define IT8152_INTC_LPNITR __REG_IT8152(0x3f00330)
|
||||
#define IT8152_INTC_LPNIAR __REG_IT8152(0x3f00334)
|
||||
#define IT8152_INTC_PDCNIRR __REG_IT8152(0x3f00340)
|
||||
#define IT8152_INTC_PDPNIRR __REG_IT8152(0x3f00344)
|
||||
#define IT8152_INTC_PDCNIMR __REG_IT8152(0x3f00348)
|
||||
#define IT8152_INTC_PDPNIMR __REG_IT8152(0x3f0034C)
|
||||
#define IT8152_INTC_PDNITR __REG_IT8152(0x3f00350)
|
||||
#define IT8152_INTC_PDNIAR __REG_IT8152(0x3f00354)
|
||||
#define IT8152_INTC_INTC_TYPER __REG_IT8152(0x3f003FC)
|
||||
|
||||
#define IT8152_GPIO_GPDR __REG_IT8152(0x3f00500)
|
||||
|
||||
/*
|
||||
Interrup contoler per register summary:
|
||||
---------------------------------------
|
||||
LCDNIRR:
|
||||
IT8152_LD_IRQ(8) PCICLK stop
|
||||
IT8152_LD_IRQ(7) MCLK ready
|
||||
IT8152_LD_IRQ(6) s/w
|
||||
IT8152_LD_IRQ(5) UART
|
||||
IT8152_LD_IRQ(4) GPIO
|
||||
IT8152_LD_IRQ(3) TIMER 4
|
||||
IT8152_LD_IRQ(2) TIMER 3
|
||||
IT8152_LD_IRQ(1) TIMER 2
|
||||
IT8152_LD_IRQ(0) TIMER 1
|
||||
|
||||
LPCNIRR:
|
||||
IT8152_LP_IRQ(x) serial IRQ x
|
||||
|
||||
PCIDNIRR:
|
||||
IT8152_PD_IRQ(14) PCISERR
|
||||
IT8152_PD_IRQ(13) CPU/PCI bridge target abort (h2pTADR)
|
||||
IT8152_PD_IRQ(12) CPU/PCI bridge master abort (h2pMADR)
|
||||
IT8152_PD_IRQ(11) PCI INTD
|
||||
IT8152_PD_IRQ(10) PCI INTC
|
||||
IT8152_PD_IRQ(9) PCI INTB
|
||||
IT8152_PD_IRQ(8) PCI INTA
|
||||
IT8152_PD_IRQ(7) serial INTD
|
||||
IT8152_PD_IRQ(6) serial INTC
|
||||
IT8152_PD_IRQ(5) serial INTB
|
||||
IT8152_PD_IRQ(4) serial INTA
|
||||
IT8152_PD_IRQ(3) serial IRQ IOCHK (IOCHKR)
|
||||
IT8152_PD_IRQ(2) chaining DMA (CDMAR)
|
||||
IT8152_PD_IRQ(1) USB (USBR)
|
||||
IT8152_PD_IRQ(0) Audio controller (ACR)
|
||||
*/
|
||||
/* frequently used interrupts */
|
||||
#define IT8152_PCISERR IT8152_PD_IRQ(14)
|
||||
#define IT8152_H2PTADR IT8152_PD_IRQ(13)
|
||||
#define IT8152_H2PMAR IT8152_PD_IRQ(12)
|
||||
#define IT8152_PCI_INTD IT8152_PD_IRQ(11)
|
||||
#define IT8152_PCI_INTC IT8152_PD_IRQ(10)
|
||||
#define IT8152_PCI_INTB IT8152_PD_IRQ(9)
|
||||
#define IT8152_PCI_INTA IT8152_PD_IRQ(8)
|
||||
#define IT8152_CDMA_INT IT8152_PD_IRQ(2)
|
||||
#define IT8152_USB_INT IT8152_PD_IRQ(1)
|
||||
#define IT8152_AUDIO_INT IT8152_PD_IRQ(0)
|
||||
|
||||
struct pci_dev;
|
||||
struct pci_sys_data;
|
||||
|
||||
extern void it8152_irq_demux(unsigned int irq, struct irq_desc *desc);
|
||||
extern void it8152_init_irq(void);
|
||||
extern int it8152_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin);
|
||||
extern int it8152_pci_setup(int nr, struct pci_sys_data *sys);
|
||||
extern struct pci_bus *it8152_pci_scan_bus(int nr, struct pci_sys_data *sys);
|
||||
|
||||
#endif /* __ASM_HARDWARE_IT8152_H */
|
||||
@ -8,10 +8,17 @@
|
||||
|
||||
#define pcibios_scan_all_fns(a, b) 0
|
||||
|
||||
#ifdef CONFIG_PCI_HOST_ITE8152
|
||||
/* ITE bridge requires setting latency timer to avoid early bus access
|
||||
termination by PIC bus mater devices
|
||||
*/
|
||||
extern void pcibios_set_master(struct pci_dev *dev);
|
||||
#else
|
||||
static inline void pcibios_set_master(struct pci_dev *dev)
|
||||
{
|
||||
/* No special bus mastering setup handling */
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline void pcibios_penalize_isa_irq(int irq, int active)
|
||||
{
|
||||
|
||||
@ -1631,6 +1631,7 @@
|
||||
#define PCI_DEVICE_ID_ITE_8211 0x8211
|
||||
#define PCI_DEVICE_ID_ITE_8212 0x8212
|
||||
#define PCI_DEVICE_ID_ITE_8213 0x8213
|
||||
#define PCI_DEVICE_ID_ITE_8152 0x8152
|
||||
#define PCI_DEVICE_ID_ITE_8872 0x8872
|
||||
#define PCI_DEVICE_ID_ITE_IT8330G_0 0xe886
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user