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net: micrel: Add support for lan8841 PHY
The LAN8841 is completely integrated triple-speed (10BASE-T/ 100BASE-TX/ 1000BASE-T) Ethernet physical layer transceivers for transmission and reception of data on standard CAT-5, as well as CAT-5e and CAT-6, unshielded twisted pair (UTP) cables. The LAN8841 offers the industry-standard GMII/MII as well as the RGMII. Some of the features of the PHY are: - Wake on LAN - Auto-MDIX - IEEE 1588-2008 (V2) - LinkMD Capable diagnosis Currently the patch offers support only for link configuration. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Horatiu Vultur
David S. Miller
parent
9ed138ff37
commit
a8f1a19d27
@ -268,6 +268,9 @@ struct kszphy_type {
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u16 interrupt_level_mask;
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u16 cable_diag_reg;
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unsigned long pair_mask;
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u16 disable_dll_tx_bit;
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u16 disable_dll_rx_bit;
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u16 disable_dll_mask;
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bool has_broadcast_disable;
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bool has_nand_tree_disable;
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bool has_rmii_ref_clk_sel;
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@ -364,6 +367,19 @@ static const struct kszphy_type ksz9021_type = {
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.interrupt_level_mask = BIT(14),
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};
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static const struct kszphy_type ksz9131_type = {
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.interrupt_level_mask = BIT(14),
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.disable_dll_tx_bit = BIT(12),
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.disable_dll_rx_bit = BIT(12),
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.disable_dll_mask = BIT_MASK(12),
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};
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static const struct kszphy_type lan8841_type = {
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.disable_dll_tx_bit = BIT(14),
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.disable_dll_rx_bit = BIT(14),
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.disable_dll_mask = BIT_MASK(14),
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};
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static int kszphy_extended_write(struct phy_device *phydev,
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u32 regnum, u16 val)
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{
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@ -1172,19 +1188,18 @@ static int ksz9131_of_load_skew_values(struct phy_device *phydev,
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#define KSZ9131RN_MMD_COMMON_CTRL_REG 2
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#define KSZ9131RN_RXC_DLL_CTRL 76
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#define KSZ9131RN_TXC_DLL_CTRL 77
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#define KSZ9131RN_DLL_CTRL_BYPASS BIT_MASK(12)
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#define KSZ9131RN_DLL_ENABLE_DELAY 0
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#define KSZ9131RN_DLL_DISABLE_DELAY BIT(12)
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static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
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{
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const struct kszphy_type *type = phydev->drv->driver_data;
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u16 rxcdll_val, txcdll_val;
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int ret;
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switch (phydev->interface) {
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case PHY_INTERFACE_MODE_RGMII:
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rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
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txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
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rxcdll_val = type->disable_dll_rx_bit;
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txcdll_val = type->disable_dll_tx_bit;
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break;
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case PHY_INTERFACE_MODE_RGMII_ID:
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rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
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@ -1192,10 +1207,10 @@ static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
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break;
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case PHY_INTERFACE_MODE_RGMII_RXID:
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rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
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txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
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txcdll_val = type->disable_dll_tx_bit;
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break;
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case PHY_INTERFACE_MODE_RGMII_TXID:
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rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
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rxcdll_val = type->disable_dll_rx_bit;
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txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
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break;
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default:
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@ -1203,13 +1218,13 @@ static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
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}
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ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
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KSZ9131RN_RXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
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KSZ9131RN_RXC_DLL_CTRL, type->disable_dll_mask,
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rxcdll_val);
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if (ret < 0)
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return ret;
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return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
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KSZ9131RN_TXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
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KSZ9131RN_TXC_DLL_CTRL, type->disable_dll_mask,
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txcdll_val);
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}
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@ -3152,6 +3167,146 @@ static int lan8814_probe(struct phy_device *phydev)
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return 0;
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}
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#define LAN8841_MMD_TIMER_REG 0
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#define LAN8841_MMD0_REGISTER_17 17
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#define LAN8841_MMD0_REGISTER_17_DROP_OPT(x) ((x) & 0x3)
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#define LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS BIT(3)
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#define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG 2
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#define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK BIT(14)
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#define LAN8841_MMD_ANALOG_REG 28
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#define LAN8841_ANALOG_CONTROL_1 1
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#define LAN8841_ANALOG_CONTROL_1_PLL_TRIM(x) (((x) & 0x3) << 5)
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#define LAN8841_ANALOG_CONTROL_10 13
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#define LAN8841_ANALOG_CONTROL_10_PLL_DIV(x) ((x) & 0x3)
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#define LAN8841_ANALOG_CONTROL_11 14
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#define LAN8841_ANALOG_CONTROL_11_LDO_REF(x) (((x) & 0x7) << 12)
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#define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT 69
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#define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL 0xbffc
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#define LAN8841_BTRX_POWER_DOWN 70
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#define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A BIT(0)
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#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_A BIT(1)
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#define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B BIT(2)
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#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_B BIT(3)
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#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_C BIT(5)
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#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_D BIT(7)
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#define LAN8841_ADC_CHANNEL_MASK 198
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static int lan8841_config_init(struct phy_device *phydev)
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{
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int ret;
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ret = ksz9131_config_init(phydev);
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if (ret)
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return ret;
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/* 100BT Clause 40 improvenent errata */
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phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
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LAN8841_ANALOG_CONTROL_1,
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LAN8841_ANALOG_CONTROL_1_PLL_TRIM(0x2));
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phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
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LAN8841_ANALOG_CONTROL_10,
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LAN8841_ANALOG_CONTROL_10_PLL_DIV(0x1));
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/* 10M/100M Ethernet Signal Tuning Errata for Shorted-Center Tap
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* Magnetics
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*/
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ret = phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
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LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG);
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if (ret & LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK) {
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phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
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LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT,
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LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL);
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phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
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LAN8841_BTRX_POWER_DOWN,
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LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A |
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LAN8841_BTRX_POWER_DOWN_BTRX_CH_A |
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LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B |
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LAN8841_BTRX_POWER_DOWN_BTRX_CH_B |
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LAN8841_BTRX_POWER_DOWN_BTRX_CH_C |
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LAN8841_BTRX_POWER_DOWN_BTRX_CH_D);
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}
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/* LDO Adjustment errata */
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phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
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LAN8841_ANALOG_CONTROL_11,
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LAN8841_ANALOG_CONTROL_11_LDO_REF(1));
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/* 100BT RGMII latency tuning errata */
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phy_write_mmd(phydev, MDIO_MMD_PMAPMD,
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LAN8841_ADC_CHANNEL_MASK, 0x0);
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phy_write_mmd(phydev, LAN8841_MMD_TIMER_REG,
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LAN8841_MMD0_REGISTER_17,
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LAN8841_MMD0_REGISTER_17_DROP_OPT(2) |
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LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS);
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return 0;
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}
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#define LAN8841_OUTPUT_CTRL 25
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#define LAN8841_OUTPUT_CTRL_INT_BUFFER BIT(14)
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static int lan8841_config_intr(struct phy_device *phydev)
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{
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int err;
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phy_modify(phydev, LAN8841_OUTPUT_CTRL,
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LAN8841_OUTPUT_CTRL_INT_BUFFER, 0);
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
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err = phy_read(phydev, LAN8814_INTS);
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if (err)
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return err;
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err = phy_write(phydev, LAN8814_INTC,
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LAN8814_INT_LINK);
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} else {
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err = phy_write(phydev, LAN8814_INTC, 0);
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if (err)
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return err;
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err = phy_read(phydev, LAN8814_INTS);
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}
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return err;
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}
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static irqreturn_t lan8841_handle_interrupt(struct phy_device *phydev)
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{
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int irq_status;
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irq_status = phy_read(phydev, LAN8814_INTS);
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if (irq_status < 0) {
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phy_error(phydev);
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return IRQ_NONE;
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}
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if (irq_status & LAN8814_INT_LINK) {
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phy_trigger_machine(phydev);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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#define LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER 3
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#define LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER_STRAP_RGMII_EN BIT(0)
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static int lan8841_probe(struct phy_device *phydev)
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{
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int err;
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err = kszphy_probe(phydev);
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if (err)
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return err;
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if (phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
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LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER) &
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LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER_STRAP_RGMII_EN)
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phydev->interface = PHY_INTERFACE_MODE_RGMII_RXID;
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return 0;
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}
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static struct phy_driver ksphy_driver[] = {
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{
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.phy_id = PHY_ID_KS8737,
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@ -3361,13 +3516,28 @@ static struct phy_driver ksphy_driver[] = {
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.resume = kszphy_resume,
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.config_intr = lan8804_config_intr,
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.handle_interrupt = lan8804_handle_interrupt,
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}, {
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.phy_id = PHY_ID_LAN8841,
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.phy_id_mask = MICREL_PHY_ID_MASK,
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.name = "Microchip LAN8841 Gigabit PHY",
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.driver_data = &lan8841_type,
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.config_init = lan8841_config_init,
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.probe = lan8841_probe,
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.soft_reset = genphy_soft_reset,
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.config_intr = lan8841_config_intr,
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.handle_interrupt = lan8841_handle_interrupt,
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.get_sset_count = kszphy_get_sset_count,
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.get_strings = kszphy_get_strings,
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.get_stats = kszphy_get_stats,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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}, {
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.phy_id = PHY_ID_KSZ9131,
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.phy_id_mask = MICREL_PHY_ID_MASK,
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.name = "Microchip KSZ9131 Gigabit PHY",
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/* PHY_GBIT_FEATURES */
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.flags = PHY_POLL_CABLE_TEST,
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.driver_data = &ksz9021_type,
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.driver_data = &ksz9131_type,
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.probe = kszphy_probe,
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.config_init = ksz9131_config_init,
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.config_intr = kszphy_config_intr,
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@ -3446,6 +3616,7 @@ static struct mdio_device_id __maybe_unused micrel_tbl[] = {
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{ PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
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{ PHY_ID_LAN8814, MICREL_PHY_ID_MASK },
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{ PHY_ID_LAN8804, MICREL_PHY_ID_MASK },
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{ PHY_ID_LAN8841, MICREL_PHY_ID_MASK },
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{ }
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};
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@ -31,6 +31,7 @@
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#define PHY_ID_KSZ9131 0x00221640
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#define PHY_ID_LAN8814 0x00221660
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#define PHY_ID_LAN8804 0x00221670
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#define PHY_ID_LAN8841 0x00221650
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#define PHY_ID_KSZ886X 0x00221430
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#define PHY_ID_KSZ8863 0x00221435
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