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Reset controller changes for v3.19
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJUctX9AAoJEFDCiBxwnmDrYzQQANVqyYFY/VRMvS5pPuPuA51L K5NQRZ7AFpZCCyfYffiC8DfFHB4WibfXUUwT8ElJVFgRnzs7u3OmMX7rKbFR0QfY rtt1nhrG77SP+/rriE9uc+mHOBO0+pauEsRROqOJleqEWwO4jXUz/g6x/34IRcuC CFrLqz/bhmn7w9eTz27UnVwJSJMNvAVpnBIScSMClZFWtmNIF8pMgqjDqOc8XF2U 2k7vMU0Af2BGkyKdrvqKcSOUoF16iC18rbuj6EBOHR87Ymd2s4gqZ5jcDv3kww7K /TVV9gIeS5zFXpK8obSMkvVsRhfZmJzbdRyj2tZQD8vh1KRA+Efiq5Jsq9m+iztN kyCpwnt3FX7KHgXlj/8m2aDOTd4HjT4x4661CMTHSbYDvRVxWkJS7eLcCKwt/F9Z o6lYw0AOiCC8tP21wK5xjxuYlbmnWKQIkIHE8JPZkRSw9bcGB4UgMsy0/4iHbUoW T9YtvAE2qSJOrER1xHRnl1dfFMhIHVX4XaOCbb3EnOSlSxQMmyzJJZUHwSUwdr1I IXxW+3Wc41Rqklv8PQbI0Gv6/hR+Tb8BMB8r0dq4qeCfdobFTEvtGuLa0KSeFXgy 439aM2zSUIXAYOOEyG7GsUkgaMj1enQsj/azB6aJl5C6yWBdFcF5ZcTM0uTbwuKt Xcs/9Nu7BNTDo3UcPhBx =FuM7 -----END PGP SIGNATURE----- Merge tag 'reset-for-3.19-2' of git://git.pengutronix.de/git/pza/linux into next/drivers Pull "Reset controller changes for v3.19" from Philipp Zabel: This adds a new driver for the sti soc family, and creates a reset_control_status interface, which is added to the existing drivers. * tag 'reset-for-3.19-2' of git://git.pengutronix.de/git/pza/linux: reset: add socfpga_reset_status reset: sti: Document sti-picophyreset controllers bindings. reset: stih407: Add softreset, powerdown and picophy controllers reset: stih407: Add reset controllers DT bindings reset: add reset_control_status helper function Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
a8afa2645c
@ -0,0 +1,42 @@
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STMicroelectronics STi family Sysconfig Picophy SoftReset Controller
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=============================================================================
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This binding describes a reset controller device that is used to enable and
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disable on-chip PicoPHY USB2 phy(s) using "softreset" control bits found in
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the STi family SoC system configuration registers.
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The actual action taken when softreset is asserted is hardware dependent.
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However, when asserted it may not be possible to access the hardware's
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registers and after an assert/deassert sequence the hardware's previous state
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may no longer be valid.
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Please refer to Documentation/devicetree/bindings/reset/reset.txt
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for common reset controller binding usage.
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Required properties:
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- compatible: Should be "st,stih407-picophyreset"
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- #reset-cells: 1, see below
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Example:
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picophyreset: picophyreset-controller {
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compatible = "st,stih407-picophyreset";
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#reset-cells = <1>;
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};
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Specifying picophyreset control of devices
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=======================================
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Device nodes should specify the reset channel required in their "resets"
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property, containing a phandle to the picophyreset device node and an
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index specifying which channel to use, as described in
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Documentation/devicetree/bindings/reset/reset.txt.
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Example:
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usb2_picophy0: usbpicophy@0 {
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resets = <&picophyreset STIH407_PICOPHY0_RESET>;
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};
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Macro definitions for the supported reset channels can be found in:
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include/dt-bindings/reset-controller/stih407-resets.h
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@ -125,6 +125,21 @@ int reset_control_deassert(struct reset_control *rstc)
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}
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EXPORT_SYMBOL_GPL(reset_control_deassert);
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/**
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* reset_control_status - returns a negative errno if not supported, a
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* positive value if the reset line is asserted, or zero if the reset
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* line is not asserted.
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* @rstc: reset controller
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*/
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int reset_control_status(struct reset_control *rstc)
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{
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if (rstc->rcdev->ops->status)
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return rstc->rcdev->ops->status(rstc->rcdev, rstc->id);
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return -ENOSYS;
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}
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EXPORT_SYMBOL_GPL(reset_control_status);
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/**
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* of_reset_control_get - Lookup and obtain a reference to a reset controller.
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* @node: device to be reset by the controller
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@ -76,9 +76,24 @@ static int socfpga_reset_deassert(struct reset_controller_dev *rcdev,
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return 0;
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}
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static int socfpga_reset_status(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct socfpga_reset_data *data = container_of(rcdev,
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struct socfpga_reset_data, rcdev);
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int bank = id / BITS_PER_LONG;
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int offset = id % BITS_PER_LONG;
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u32 reg;
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reg = readl(data->membase + OFFSET_MODRST + (bank * NR_BANKS));
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return !(reg & BIT(offset));
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}
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static struct reset_control_ops socfpga_reset_ops = {
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.assert = socfpga_reset_assert,
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.deassert = socfpga_reset_deassert,
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.status = socfpga_reset_status,
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};
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static int socfpga_reset_probe(struct platform_device *pdev)
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@ -12,4 +12,8 @@ config STIH416_RESET
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bool
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select STI_RESET_SYSCFG
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config STIH407_RESET
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bool
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select STI_RESET_SYSCFG
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endif
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@ -2,3 +2,4 @@ obj-$(CONFIG_STI_RESET_SYSCFG) += reset-syscfg.o
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obj-$(CONFIG_STIH415_RESET) += reset-stih415.o
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obj-$(CONFIG_STIH416_RESET) += reset-stih416.o
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obj-$(CONFIG_STIH407_RESET) += reset-stih407.o
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158
drivers/reset/sti/reset-stih407.c
Normal file
158
drivers/reset/sti/reset-stih407.c
Normal file
@ -0,0 +1,158 @@
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/*
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* Copyright (C) 2014 STMicroelectronics (R&D) Limited
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* Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/reset-controller/stih407-resets.h>
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#include "reset-syscfg.h"
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/* STiH407 Peripheral powerdown definitions. */
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static const char stih407_core[] = "st,stih407-core-syscfg";
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static const char stih407_sbc_reg[] = "st,stih407-sbc-reg-syscfg";
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static const char stih407_lpm[] = "st,stih407-lpm-syscfg";
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#define STIH407_PDN_0(_bit) \
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_SYSCFG_RST_CH(stih407_core, SYSCFG_5000, _bit, SYSSTAT_5500, _bit)
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#define STIH407_PDN_1(_bit) \
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_SYSCFG_RST_CH(stih407_core, SYSCFG_5001, _bit, SYSSTAT_5501, _bit)
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#define STIH407_PDN_ETH(_bit, _stat) \
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_SYSCFG_RST_CH(stih407_sbc_reg, SYSCFG_4032, _bit, SYSSTAT_4520, _stat)
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/* Powerdown requests control 0 */
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#define SYSCFG_5000 0x0
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#define SYSSTAT_5500 0x7d0
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/* Powerdown requests control 1 (High Speed Links) */
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#define SYSCFG_5001 0x4
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#define SYSSTAT_5501 0x7d4
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/* Ethernet powerdown/status/reset */
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#define SYSCFG_4032 0x80
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#define SYSSTAT_4520 0x820
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#define SYSCFG_4002 0x8
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static const struct syscfg_reset_channel_data stih407_powerdowns[] = {
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[STIH407_EMISS_POWERDOWN] = STIH407_PDN_0(1),
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[STIH407_NAND_POWERDOWN] = STIH407_PDN_0(0),
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[STIH407_USB3_POWERDOWN] = STIH407_PDN_1(6),
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[STIH407_USB2_PORT1_POWERDOWN] = STIH407_PDN_1(5),
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[STIH407_USB2_PORT0_POWERDOWN] = STIH407_PDN_1(4),
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[STIH407_PCIE1_POWERDOWN] = STIH407_PDN_1(3),
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[STIH407_PCIE0_POWERDOWN] = STIH407_PDN_1(2),
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[STIH407_SATA1_POWERDOWN] = STIH407_PDN_1(1),
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[STIH407_SATA0_POWERDOWN] = STIH407_PDN_1(0),
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[STIH407_ETH1_POWERDOWN] = STIH407_PDN_ETH(0, 2),
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};
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/* Reset Generator control 0/1 */
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#define SYSCFG_5131 0x20c
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#define SYSCFG_5132 0x210
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#define LPM_SYSCFG_1 0x4 /* Softreset IRB & SBC UART */
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#define STIH407_SRST_CORE(_reg, _bit) \
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_SYSCFG_RST_CH_NO_ACK(stih407_core, _reg, _bit)
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#define STIH407_SRST_SBC(_reg, _bit) \
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_SYSCFG_RST_CH_NO_ACK(stih407_sbc_reg, _reg, _bit)
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#define STIH407_SRST_LPM(_reg, _bit) \
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_SYSCFG_RST_CH_NO_ACK(stih407_lpm, _reg, _bit)
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static const struct syscfg_reset_channel_data stih407_softresets[] = {
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[STIH407_ETH1_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 4),
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[STIH407_MMC1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 3),
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[STIH407_USB2_PORT0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 28),
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[STIH407_USB2_PORT1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 29),
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[STIH407_PICOPHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 30),
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[STIH407_IRB_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 6),
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[STIH407_PCIE0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 6),
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[STIH407_PCIE1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 15),
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[STIH407_SATA0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 7),
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[STIH407_SATA1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 16),
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[STIH407_MIPHY0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 4),
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[STIH407_MIPHY1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 13),
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[STIH407_MIPHY2_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 22),
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[STIH407_SATA0_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 5),
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[STIH407_SATA1_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 14),
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[STIH407_DELTA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 3),
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[STIH407_BLITTER_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 10),
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[STIH407_HDTVOUT_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 11),
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[STIH407_HDQVDP_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 12),
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[STIH407_VDP_AUX_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 14),
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[STIH407_COMPO_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 15),
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[STIH407_HDMI_TX_PHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 21),
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[STIH407_JPEG_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 23),
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[STIH407_VP8_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 24),
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[STIH407_GPU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 30),
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[STIH407_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 0),
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[STIH407_ERAM_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 1),
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[STIH407_LPM_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 2),
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[STIH407_KEYSCAN_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 8),
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};
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/* PicoPHY reset/control */
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#define SYSCFG_5061 0x0f4
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static const struct syscfg_reset_channel_data stih407_picophyresets[] = {
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[STIH407_PICOPHY0_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 5),
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[STIH407_PICOPHY1_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 6),
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[STIH407_PICOPHY2_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 7),
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};
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static const struct syscfg_reset_controller_data stih407_powerdown_controller = {
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.wait_for_ack = true,
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.nr_channels = ARRAY_SIZE(stih407_powerdowns),
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.channels = stih407_powerdowns,
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};
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static const struct syscfg_reset_controller_data stih407_softreset_controller = {
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.wait_for_ack = false,
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.active_low = true,
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.nr_channels = ARRAY_SIZE(stih407_softresets),
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.channels = stih407_softresets,
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};
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static const struct syscfg_reset_controller_data stih407_picophyreset_controller = {
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.wait_for_ack = false,
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.nr_channels = ARRAY_SIZE(stih407_picophyresets),
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.channels = stih407_picophyresets,
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};
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static struct of_device_id stih407_reset_match[] = {
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{
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.compatible = "st,stih407-powerdown",
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.data = &stih407_powerdown_controller,
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},
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{
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.compatible = "st,stih407-softreset",
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.data = &stih407_softreset_controller,
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},
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{
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.compatible = "st,stih407-picophyreset",
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.data = &stih407_picophyreset_controller,
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},
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{ /* sentinel */ },
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};
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static struct platform_driver stih407_reset_driver = {
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.probe = syscfg_reset_probe,
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.driver = {
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.name = "reset-stih407",
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.of_match_table = stih407_reset_match,
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},
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};
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static int __init stih407_reset_init(void)
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{
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return platform_driver_register(&stih407_reset_driver);
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}
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arch_initcall(stih407_reset_init);
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61
include/dt-bindings/reset-controller/stih407-resets.h
Normal file
61
include/dt-bindings/reset-controller/stih407-resets.h
Normal file
@ -0,0 +1,61 @@
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/*
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* This header provides constants for the reset controller
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* based peripheral powerdown requests on the STMicroelectronics
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* STiH407 SoC.
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*/
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#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH407
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#define _DT_BINDINGS_RESET_CONTROLLER_STIH407
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/* Powerdown requests control 0 */
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#define STIH407_EMISS_POWERDOWN 0
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#define STIH407_NAND_POWERDOWN 1
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/* Synp GMAC PowerDown */
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#define STIH407_ETH1_POWERDOWN 2
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/* Powerdown requests control 1 */
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#define STIH407_USB3_POWERDOWN 3
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#define STIH407_USB2_PORT1_POWERDOWN 4
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#define STIH407_USB2_PORT0_POWERDOWN 5
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#define STIH407_PCIE1_POWERDOWN 6
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#define STIH407_PCIE0_POWERDOWN 7
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#define STIH407_SATA1_POWERDOWN 8
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#define STIH407_SATA0_POWERDOWN 9
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/* Reset defines */
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#define STIH407_ETH1_SOFTRESET 0
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#define STIH407_MMC1_SOFTRESET 1
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#define STIH407_PICOPHY_SOFTRESET 2
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#define STIH407_IRB_SOFTRESET 3
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#define STIH407_PCIE0_SOFTRESET 4
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#define STIH407_PCIE1_SOFTRESET 5
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#define STIH407_SATA0_SOFTRESET 6
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#define STIH407_SATA1_SOFTRESET 7
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#define STIH407_MIPHY0_SOFTRESET 8
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#define STIH407_MIPHY1_SOFTRESET 9
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#define STIH407_MIPHY2_SOFTRESET 10
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#define STIH407_SATA0_PWR_SOFTRESET 11
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#define STIH407_SATA1_PWR_SOFTRESET 12
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#define STIH407_DELTA_SOFTRESET 13
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#define STIH407_BLITTER_SOFTRESET 14
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#define STIH407_HDTVOUT_SOFTRESET 15
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#define STIH407_HDQVDP_SOFTRESET 16
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#define STIH407_VDP_AUX_SOFTRESET 17
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#define STIH407_COMPO_SOFTRESET 18
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#define STIH407_HDMI_TX_PHY_SOFTRESET 19
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#define STIH407_JPEG_DEC_SOFTRESET 20
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#define STIH407_VP8_DEC_SOFTRESET 21
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#define STIH407_GPU_SOFTRESET 22
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#define STIH407_HVA_SOFTRESET 23
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#define STIH407_ERAM_HVA_SOFTRESET 24
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#define STIH407_LPM_SOFTRESET 25
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#define STIH407_KEYSCAN_SOFTRESET 26
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#define STIH407_USB2_PORT0_SOFTRESET 27
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#define STIH407_USB2_PORT1_SOFTRESET 28
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/* Picophy reset defines */
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#define STIH407_PICOPHY0_RESET 0
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#define STIH407_PICOPHY1_RESET 1
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#define STIH407_PICOPHY2_RESET 2
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#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH407 */
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@ -12,11 +12,13 @@ struct reset_controller_dev;
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* things to reset the device
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* @assert: manually assert the reset line, if supported
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* @deassert: manually deassert the reset line, if supported
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* @status: return the status of the reset line, if supported
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*/
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struct reset_control_ops {
|
||||
int (*reset)(struct reset_controller_dev *rcdev, unsigned long id);
|
||||
int (*assert)(struct reset_controller_dev *rcdev, unsigned long id);
|
||||
int (*deassert)(struct reset_controller_dev *rcdev, unsigned long id);
|
||||
int (*status)(struct reset_controller_dev *rcdev, unsigned long id);
|
||||
};
|
||||
|
||||
struct module;
|
||||
|
||||
@ -10,6 +10,7 @@ struct reset_control;
|
||||
int reset_control_reset(struct reset_control *rstc);
|
||||
int reset_control_assert(struct reset_control *rstc);
|
||||
int reset_control_deassert(struct reset_control *rstc);
|
||||
int reset_control_status(struct reset_control *rstc);
|
||||
|
||||
struct reset_control *reset_control_get(struct device *dev, const char *id);
|
||||
void reset_control_put(struct reset_control *rstc);
|
||||
@ -57,6 +58,12 @@ static inline int reset_control_deassert(struct reset_control *rstc)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int reset_control_status(struct reset_control *rstc)
|
||||
{
|
||||
WARN_ON(1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void reset_control_put(struct reset_control *rstc)
|
||||
{
|
||||
WARN_ON(1);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user