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[Blackfin] arch: fix obvious bfin_write typos
Signed-off-by: Meihui Fan <mhfan@hhcn.com> Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
This commit is contained in:
Meihui Fan
Bryan Wu
parent
37167e6411
commit
a8a46a269e
@ -290,7 +290,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
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#define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE)
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#define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val)
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#define bfin_read_EBIU_ERRADD() bfin_read32(EBIU_ERRADD)
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#define bfin_write_EBIU_ERRADD(val) bfin_write32(EBIU_ERRADD)
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#define bfin_write_EBIU_ERRADD(val) bfin_write32(EBIU_ERRADD, val)
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#define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST)
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#define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val)
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#define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL)
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@ -359,23 +359,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
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/* DMA Channel 0 Registers */
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#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
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#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR)
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#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
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#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
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#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR)
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#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
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#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
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#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
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#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
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#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
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#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
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#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY)
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#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
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#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
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#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
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#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
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#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY)
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#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
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#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
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#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR)
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#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
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#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
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#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR)
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#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
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#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
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#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
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#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
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@ -388,23 +388,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
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/* DMA Channel 1 Registers */
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#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
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#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR)
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#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
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#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
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#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR)
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#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
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#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
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#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
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#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
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#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
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#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
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#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY)
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#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
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#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
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#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
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#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
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#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY)
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#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
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#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
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#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR)
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#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
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#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
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#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR)
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#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
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#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
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#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
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#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
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@ -417,23 +417,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
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/* DMA Channel 2 Registers */
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#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
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#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR)
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#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
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#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
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#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR)
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#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
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#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
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#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
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#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
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#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
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#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
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#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY)
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#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
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#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
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#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
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#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
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#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY)
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#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
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#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
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#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR)
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#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
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#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
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#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR)
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#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
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#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
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#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
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#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
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@ -446,23 +446,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
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/* DMA Channel 3 Registers */
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#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
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#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR)
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#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
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#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
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#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR)
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#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
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#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
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#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
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#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
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#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
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#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
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#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY)
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#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
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#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
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#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
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#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
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#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY)
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#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
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#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
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#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR)
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#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
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#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
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#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR)
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#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
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#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
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#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
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#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
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@ -475,23 +475,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
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/* DMA Channel 4 Registers */
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#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
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#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR)
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#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
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#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
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#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR)
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#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
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#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
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#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
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#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
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#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
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#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
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#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY)
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#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
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#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
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#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
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#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
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#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY)
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#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
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#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
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#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR)
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#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
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#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
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#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR)
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#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
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#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
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#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
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#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
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@ -504,23 +504,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
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/* DMA Channel 5 Registers */
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#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
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#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR)
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#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
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#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
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#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR)
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#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
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#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
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#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
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#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
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#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
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#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
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#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY)
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#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
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#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
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#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
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#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
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#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY)
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#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
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#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
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#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR)
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#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
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#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
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#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR)
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#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
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#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
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#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
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#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
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@ -533,23 +533,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
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/* DMA Channel 6 Registers */
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#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
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#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR)
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#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
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#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
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#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR)
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#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
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#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
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#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
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#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
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#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
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#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
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#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY)
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#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
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#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
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#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
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#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
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#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY)
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#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
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#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
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#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR)
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#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
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#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
|
||||
#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR)
|
||||
#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
|
||||
#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
|
||||
#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
|
||||
#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
|
||||
@ -562,23 +562,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
||||
/* DMA Channel 7 Registers */
|
||||
|
||||
#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
|
||||
#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR)
|
||||
#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
|
||||
#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
|
||||
#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR)
|
||||
#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
|
||||
#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
|
||||
#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
|
||||
#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
|
||||
#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
|
||||
#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
|
||||
#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY)
|
||||
#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
|
||||
#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
|
||||
#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
|
||||
#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
|
||||
#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY)
|
||||
#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
|
||||
#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
|
||||
#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR)
|
||||
#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
|
||||
#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
|
||||
#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR)
|
||||
#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
|
||||
#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
|
||||
#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
|
||||
#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
|
||||
@ -591,23 +591,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
||||
/* DMA Channel 8 Registers */
|
||||
|
||||
#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
|
||||
#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR)
|
||||
#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
|
||||
#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
|
||||
#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR)
|
||||
#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
|
||||
#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
|
||||
#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
|
||||
#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
|
||||
#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
|
||||
#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
|
||||
#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY)
|
||||
#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
|
||||
#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
|
||||
#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
|
||||
#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
|
||||
#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY)
|
||||
#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
|
||||
#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
|
||||
#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR)
|
||||
#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
|
||||
#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
|
||||
#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR)
|
||||
#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
|
||||
#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
|
||||
#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
|
||||
#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
|
||||
@ -620,23 +620,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
||||
/* DMA Channel 9 Registers */
|
||||
|
||||
#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
|
||||
#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR)
|
||||
#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
|
||||
#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
|
||||
#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR)
|
||||
#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
|
||||
#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
|
||||
#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
|
||||
#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
|
||||
#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
|
||||
#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
|
||||
#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY)
|
||||
#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
|
||||
#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
|
||||
#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
|
||||
#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
|
||||
#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY)
|
||||
#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
|
||||
#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
|
||||
#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR)
|
||||
#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
|
||||
#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
|
||||
#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR)
|
||||
#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
|
||||
#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
|
||||
#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
|
||||
#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
|
||||
@ -649,23 +649,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
||||
/* DMA Channel 10 Registers */
|
||||
|
||||
#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
|
||||
#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR)
|
||||
#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
|
||||
#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
|
||||
#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR)
|
||||
#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
|
||||
#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
|
||||
#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
|
||||
#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
|
||||
#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
|
||||
#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
|
||||
#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY)
|
||||
#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
|
||||
#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
|
||||
#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
|
||||
#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
|
||||
#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY)
|
||||
#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
|
||||
#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
|
||||
#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR)
|
||||
#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
|
||||
#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
|
||||
#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR)
|
||||
#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
|
||||
#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
|
||||
#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
|
||||
#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
|
||||
@ -678,23 +678,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
||||
/* DMA Channel 11 Registers */
|
||||
|
||||
#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
|
||||
#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR)
|
||||
#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
|
||||
#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
|
||||
#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR)
|
||||
#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
|
||||
#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
|
||||
#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
|
||||
#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
|
||||
#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
|
||||
#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
|
||||
#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY)
|
||||
#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
|
||||
#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
|
||||
#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
|
||||
#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
|
||||
#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY)
|
||||
#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
|
||||
#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
|
||||
#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR)
|
||||
#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
|
||||
#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
|
||||
#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR)
|
||||
#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
|
||||
#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
|
||||
#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
|
||||
#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
|
||||
@ -707,7 +707,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
||||
/* MDMA Stream 0 Registers */
|
||||
|
||||
#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
|
||||
#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR)
|
||||
#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
|
||||
#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
|
||||
#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
|
||||
#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
|
||||
@ -770,11 +770,11 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
||||
#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
|
||||
#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
|
||||
#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
|
||||
#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY)
|
||||
#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
|
||||
#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
|
||||
#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
|
||||
#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
|
||||
#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY)
|
||||
#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
|
||||
#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
|
||||
#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
|
||||
#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
|
||||
@ -796,11 +796,11 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
||||
#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
|
||||
#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
|
||||
#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
|
||||
#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY)
|
||||
#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
|
||||
#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
|
||||
#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
|
||||
#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
|
||||
#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY)
|
||||
#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
|
||||
#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
|
||||
#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
|
||||
#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
|
||||
@ -1213,23 +1213,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
||||
/* DMA Channel 12 Registers */
|
||||
|
||||
#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_read32(DMA12_NEXT_DESC_PTR)
|
||||
#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR)
|
||||
#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR, val)
|
||||
#define bfin_read_DMA12_START_ADDR() bfin_read32(DMA12_START_ADDR)
|
||||
#define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR)
|
||||
#define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR, val)
|
||||
#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG)
|
||||
#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val)
|
||||
#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT)
|
||||
#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val)
|
||||
#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY)
|
||||
#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY)
|
||||
#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
|
||||
#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT)
|
||||
#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val)
|
||||
#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY)
|
||||
#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY)
|
||||
#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
|
||||
#define bfin_read_DMA12_CURR_DESC_PTR() bfin_read32(DMA12_CURR_DESC_PTR)
|
||||
#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR)
|
||||
#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR, val)
|
||||
#define bfin_read_DMA12_CURR_ADDR() bfin_read32(DMA12_CURR_ADDR)
|
||||
#define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR)
|
||||
#define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR, val)
|
||||
#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS)
|
||||
#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
|
||||
#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
|
||||
@ -1242,23 +1242,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
||||
/* DMA Channel 13 Registers */
|
||||
|
||||
#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_read32(DMA13_NEXT_DESC_PTR)
|
||||
#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR)
|
||||
#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR, val)
|
||||
#define bfin_read_DMA13_START_ADDR() bfin_read32(DMA13_START_ADDR)
|
||||
#define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR)
|
||||
#define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR, val)
|
||||
#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG)
|
||||
#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val)
|
||||
#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT)
|
||||
#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val)
|
||||
#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY)
|
||||
#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY)
|
||||
#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
|
||||
#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT)
|
||||
#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val)
|
||||
#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY)
|
||||
#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY)
|
||||
#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
|
||||
#define bfin_read_DMA13_CURR_DESC_PTR() bfin_read32(DMA13_CURR_DESC_PTR)
|
||||
#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR)
|
||||
#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR, val)
|
||||
#define bfin_read_DMA13_CURR_ADDR() bfin_read32(DMA13_CURR_ADDR)
|
||||
#define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR)
|
||||
#define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR, val)
|
||||
#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS)
|
||||
#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
|
||||
#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
|
||||
@ -1271,23 +1271,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
||||
/* DMA Channel 14 Registers */
|
||||
|
||||
#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_read32(DMA14_NEXT_DESC_PTR)
|
||||
#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR)
|
||||
#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR, val)
|
||||
#define bfin_read_DMA14_START_ADDR() bfin_read32(DMA14_START_ADDR)
|
||||
#define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR)
|
||||
#define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR, val)
|
||||
#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG)
|
||||
#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val)
|
||||
#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT)
|
||||
#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val)
|
||||
#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY)
|
||||
#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY)
|
||||
#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
|
||||
#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT)
|
||||
#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val)
|
||||
#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY)
|
||||
#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY)
|
||||
#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
|
||||
#define bfin_read_DMA14_CURR_DESC_PTR() bfin_read32(DMA14_CURR_DESC_PTR)
|
||||
#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR)
|
||||
#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR, val)
|
||||
#define bfin_read_DMA14_CURR_ADDR() bfin_read32(DMA14_CURR_ADDR)
|
||||
#define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR)
|
||||
#define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR, val)
|
||||
#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS)
|
||||
#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
|
||||
#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
|
||||
@ -1300,23 +1300,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
||||
/* DMA Channel 15 Registers */
|
||||
|
||||
#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_read32(DMA15_NEXT_DESC_PTR)
|
||||
#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR)
|
||||
#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR, val)
|
||||
#define bfin_read_DMA15_START_ADDR() bfin_read32(DMA15_START_ADDR)
|
||||
#define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR)
|
||||
#define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR, val)
|
||||
#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG)
|
||||
#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val)
|
||||
#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT)
|
||||
#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val)
|
||||
#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY)
|
||||
#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY)
|
||||
#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
|
||||
#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT)
|
||||
#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val)
|
||||
#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY)
|
||||
#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY)
|
||||
#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
|
||||
#define bfin_read_DMA15_CURR_DESC_PTR() bfin_read32(DMA15_CURR_DESC_PTR)
|
||||
#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR)
|
||||
#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR, val)
|
||||
#define bfin_read_DMA15_CURR_ADDR() bfin_read32(DMA15_CURR_ADDR)
|
||||
#define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR)
|
||||
#define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR, val)
|
||||
#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS)
|
||||
#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
|
||||
#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
|
||||
@ -1329,23 +1329,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
||||
/* DMA Channel 16 Registers */
|
||||
|
||||
#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_read32(DMA16_NEXT_DESC_PTR)
|
||||
#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR)
|
||||
#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR, val)
|
||||
#define bfin_read_DMA16_START_ADDR() bfin_read32(DMA16_START_ADDR)
|
||||
#define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR)
|
||||
#define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR, val)
|
||||
#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG)
|
||||
#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val)
|
||||
#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT)
|
||||
#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val)
|
||||
#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY)
|
||||
#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY)
|
||||
#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
|
||||
#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT)
|
||||
#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val)
|
||||
#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY)
|
||||
#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY)
|
||||
#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
|
||||
#define bfin_read_DMA16_CURR_DESC_PTR() bfin_read32(DMA16_CURR_DESC_PTR)
|
||||
#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR)
|
||||
#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR, val)
|
||||
#define bfin_read_DMA16_CURR_ADDR() bfin_read32(DMA16_CURR_ADDR)
|
||||
#define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR)
|
||||
#define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR, val)
|
||||
#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS)
|
||||
#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
|
||||
#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
|
||||
@ -1358,23 +1358,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
||||
/* DMA Channel 17 Registers */
|
||||
|
||||
#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_read32(DMA17_NEXT_DESC_PTR)
|
||||
#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR)
|
||||
#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR, val)
|
||||
#define bfin_read_DMA17_START_ADDR() bfin_read32(DMA17_START_ADDR)
|
||||
#define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR)
|
||||
#define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR, val)
|
||||
#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG)
|
||||
#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val)
|
||||
#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT)
|
||||
#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val)
|
||||
#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY)
|
||||
#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY)
|
||||
#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
|
||||
#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT)
|
||||
#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val)
|
||||
#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY)
|
||||
#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY)
|
||||
#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
|
||||
#define bfin_read_DMA17_CURR_DESC_PTR() bfin_read32(DMA17_CURR_DESC_PTR)
|
||||
#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR)
|
||||
#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR, val)
|
||||
#define bfin_read_DMA17_CURR_ADDR() bfin_read32(DMA17_CURR_ADDR)
|
||||
#define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR)
|
||||
#define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR, val)
|
||||
#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS)
|
||||
#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
|
||||
#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
|
||||
@ -1387,23 +1387,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
||||
/* DMA Channel 18 Registers */
|
||||
|
||||
#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_read32(DMA18_NEXT_DESC_PTR)
|
||||
#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR)
|
||||
#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR, val)
|
||||
#define bfin_read_DMA18_START_ADDR() bfin_read32(DMA18_START_ADDR)
|
||||
#define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR)
|
||||
#define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR, val)
|
||||
#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG)
|
||||
#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val)
|
||||
#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT)
|
||||
#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val)
|
||||
#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY)
|
||||
#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY)
|
||||
#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
|
||||
#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT)
|
||||
#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val)
|
||||
#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY)
|
||||
#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY)
|
||||
#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
|
||||
#define bfin_read_DMA18_CURR_DESC_PTR() bfin_read32(DMA18_CURR_DESC_PTR)
|
||||
#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR)
|
||||
#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR, val)
|
||||
#define bfin_read_DMA18_CURR_ADDR() bfin_read32(DMA18_CURR_ADDR)
|
||||
#define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR)
|
||||
#define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR, val)
|
||||
#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS)
|
||||
#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
|
||||
#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
|
||||
@ -1416,23 +1416,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
||||
/* DMA Channel 19 Registers */
|
||||
|
||||
#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_read32(DMA19_NEXT_DESC_PTR)
|
||||
#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR)
|
||||
#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR, val)
|
||||
#define bfin_read_DMA19_START_ADDR() bfin_read32(DMA19_START_ADDR)
|
||||
#define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR)
|
||||
#define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR, val)
|
||||
#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG)
|
||||
#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val)
|
||||
#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT)
|
||||
#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val)
|
||||
#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY)
|
||||
#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY)
|
||||
#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
|
||||
#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT)
|
||||
#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val)
|
||||
#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY)
|
||||
#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY)
|
||||
#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
|
||||
#define bfin_read_DMA19_CURR_DESC_PTR() bfin_read32(DMA19_CURR_DESC_PTR)
|
||||
#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR)
|
||||
#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR, val)
|
||||
#define bfin_read_DMA19_CURR_ADDR() bfin_read32(DMA19_CURR_ADDR)
|
||||
#define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR)
|
||||
#define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR, val)
|
||||
#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS)
|
||||
#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
|
||||
#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
|
||||
@ -1445,23 +1445,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
||||
/* DMA Channel 20 Registers */
|
||||
|
||||
#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_read32(DMA20_NEXT_DESC_PTR)
|
||||
#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR)
|
||||
#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR, val)
|
||||
#define bfin_read_DMA20_START_ADDR() bfin_read32(DMA20_START_ADDR)
|
||||
#define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR)
|
||||
#define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR, val)
|
||||
#define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG)
|
||||
#define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val)
|
||||
#define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT)
|
||||
#define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val)
|
||||
#define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY)
|
||||
#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY)
|
||||
#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
|
||||
#define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT)
|
||||
#define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val)
|
||||
#define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY)
|
||||
#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY)
|
||||
#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
|
||||
#define bfin_read_DMA20_CURR_DESC_PTR() bfin_read32(DMA20_CURR_DESC_PTR)
|
||||
#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR)
|
||||
#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR, val)
|
||||
#define bfin_read_DMA20_CURR_ADDR() bfin_read32(DMA20_CURR_ADDR)
|
||||
#define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR)
|
||||
#define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR, val)
|
||||
#define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS)
|
||||
#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
|
||||
#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
|
||||
@ -1474,23 +1474,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
||||
/* DMA Channel 21 Registers */
|
||||
|
||||
#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_read32(DMA21_NEXT_DESC_PTR)
|
||||
#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_write32(DMA21_NEXT_DESC_PTR)
|
||||
#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_write32(DMA21_NEXT_DESC_PTR, val)
|
||||
#define bfin_read_DMA21_START_ADDR() bfin_read32(DMA21_START_ADDR)
|
||||
#define bfin_write_DMA21_START_ADDR(val) bfin_write32(DMA21_START_ADDR)
|
||||
#define bfin_write_DMA21_START_ADDR(val) bfin_write32(DMA21_START_ADDR, val)
|
||||
#define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG)
|
||||
#define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val)
|
||||
#define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT)
|
||||
#define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val)
|
||||
#define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY)
|
||||
#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY)
|
||||
#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
|
||||
#define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT)
|
||||
#define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val)
|
||||
#define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY)
|
||||
#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY)
|
||||
#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
|
||||
#define bfin_read_DMA21_CURR_DESC_PTR() bfin_read32(DMA21_CURR_DESC_PTR)
|
||||
#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_write32(DMA21_CURR_DESC_PTR)
|
||||
#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_write32(DMA21_CURR_DESC_PTR, val)
|
||||
#define bfin_read_DMA21_CURR_ADDR() bfin_read32(DMA21_CURR_ADDR)
|
||||
#define bfin_write_DMA21_CURR_ADDR(val) bfin_write32(DMA21_CURR_ADDR)
|
||||
#define bfin_write_DMA21_CURR_ADDR(val) bfin_write32(DMA21_CURR_ADDR, val)
|
||||
#define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS)
|
||||
#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
|
||||
#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
|
||||
@ -1503,23 +1503,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
||||
/* DMA Channel 22 Registers */
|
||||
|
||||
#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_read32(DMA22_NEXT_DESC_PTR)
|
||||
#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_write32(DMA22_NEXT_DESC_PTR)
|
||||
#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_write32(DMA22_NEXT_DESC_PTR, val)
|
||||
#define bfin_read_DMA22_START_ADDR() bfin_read32(DMA22_START_ADDR)
|
||||
#define bfin_write_DMA22_START_ADDR(val) bfin_write32(DMA22_START_ADDR)
|
||||
#define bfin_write_DMA22_START_ADDR(val) bfin_write32(DMA22_START_ADDR, val)
|
||||
#define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG)
|
||||
#define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val)
|
||||
#define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT)
|
||||
#define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val)
|
||||
#define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY)
|
||||
#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY)
|
||||
#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
|
||||
#define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT)
|
||||
#define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val)
|
||||
#define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY)
|
||||
#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY)
|
||||
#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
|
||||
#define bfin_read_DMA22_CURR_DESC_PTR() bfin_read32(DMA22_CURR_DESC_PTR)
|
||||
#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_write32(DMA22_CURR_DESC_PTR)
|
||||
#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_write32(DMA22_CURR_DESC_PTR, val)
|
||||
#define bfin_read_DMA22_CURR_ADDR() bfin_read32(DMA22_CURR_ADDR)
|
||||
#define bfin_write_DMA22_CURR_ADDR(val) bfin_write32(DMA22_CURR_ADDR)
|
||||
#define bfin_write_DMA22_CURR_ADDR(val) bfin_write32(DMA22_CURR_ADDR, val)
|
||||
#define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS)
|
||||
#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
|
||||
#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
|
||||
@ -1532,23 +1532,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
||||
/* DMA Channel 23 Registers */
|
||||
|
||||
#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_read32(DMA23_NEXT_DESC_PTR)
|
||||
#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_write32(DMA23_NEXT_DESC_PTR)
|
||||
#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_write32(DMA23_NEXT_DESC_PTR, val)
|
||||
#define bfin_read_DMA23_START_ADDR() bfin_read32(DMA23_START_ADDR)
|
||||
#define bfin_write_DMA23_START_ADDR(val) bfin_write32(DMA23_START_ADDR)
|
||||
#define bfin_write_DMA23_START_ADDR(val) bfin_write32(DMA23_START_ADDR, val)
|
||||
#define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG)
|
||||
#define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val)
|
||||
#define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT)
|
||||
#define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val)
|
||||
#define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY)
|
||||
#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY)
|
||||
#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
|
||||
#define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT)
|
||||
#define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val)
|
||||
#define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY)
|
||||
#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY)
|
||||
#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
|
||||
#define bfin_read_DMA23_CURR_DESC_PTR() bfin_read32(DMA23_CURR_DESC_PTR)
|
||||
#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_write32(DMA23_CURR_DESC_PTR)
|
||||
#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_write32(DMA23_CURR_DESC_PTR, val)
|
||||
#define bfin_read_DMA23_CURR_ADDR() bfin_read32(DMA23_CURR_ADDR)
|
||||
#define bfin_write_DMA23_CURR_ADDR(val) bfin_write32(DMA23_CURR_ADDR)
|
||||
#define bfin_write_DMA23_CURR_ADDR(val) bfin_write32(DMA23_CURR_ADDR, val)
|
||||
#define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS)
|
||||
#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
|
||||
#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
|
||||
@ -1561,23 +1561,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
||||
/* MDMA Stream 2 Registers */
|
||||
|
||||
#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_read32(MDMA_D2_NEXT_DESC_PTR)
|
||||
#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR)
|
||||
#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR, val)
|
||||
#define bfin_read_MDMA_D2_START_ADDR() bfin_read32(MDMA_D2_START_ADDR)
|
||||
#define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR)
|
||||
#define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR, val)
|
||||
#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG)
|
||||
#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
|
||||
#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT)
|
||||
#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
|
||||
#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY)
|
||||
#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY)
|
||||
#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
|
||||
#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT)
|
||||
#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
|
||||
#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY)
|
||||
#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY)
|
||||
#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
|
||||
#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_read32(MDMA_D2_CURR_DESC_PTR)
|
||||
#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR)
|
||||
#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR, val)
|
||||
#define bfin_read_MDMA_D2_CURR_ADDR() bfin_read32(MDMA_D2_CURR_ADDR)
|
||||
#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR)
|
||||
#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR, val)
|
||||
#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
|
||||
#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
|
||||
#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
|
||||
@ -1587,23 +1587,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
||||
#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
|
||||
#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
|
||||
#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_read32(MDMA_S2_NEXT_DESC_PTR)
|
||||
#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR)
|
||||
#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR, val)
|
||||
#define bfin_read_MDMA_S2_START_ADDR() bfin_read32(MDMA_S2_START_ADDR)
|
||||
#define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR)
|
||||
#define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR, val)
|
||||
#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG)
|
||||
#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
|
||||
#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT)
|
||||
#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
|
||||
#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY)
|
||||
#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY)
|
||||
#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
|
||||
#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT)
|
||||
#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
|
||||
#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY)
|
||||
#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY)
|
||||
#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
|
||||
#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_read32(MDMA_S2_CURR_DESC_PTR)
|
||||
#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR)
|
||||
#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR, val)
|
||||
#define bfin_read_MDMA_S2_CURR_ADDR() bfin_read32(MDMA_S2_CURR_ADDR)
|
||||
#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR)
|
||||
#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR, val)
|
||||
#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
|
||||
#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
|
||||
#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
|
||||
@ -1616,23 +1616,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
||||
/* MDMA Stream 3 Registers */
|
||||
|
||||
#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_read32(MDMA_D3_NEXT_DESC_PTR)
|
||||
#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR)
|
||||
#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR, val)
|
||||
#define bfin_read_MDMA_D3_START_ADDR() bfin_read32(MDMA_D3_START_ADDR)
|
||||
#define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR)
|
||||
#define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR, val)
|
||||
#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG)
|
||||
#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
|
||||
#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT)
|
||||
#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
|
||||
#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY)
|
||||
#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY)
|
||||
#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
|
||||
#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT)
|
||||
#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
|
||||
#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY)
|
||||
#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY)
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#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
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#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_read32(MDMA_D3_CURR_DESC_PTR)
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#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR)
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#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR, val)
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#define bfin_read_MDMA_D3_CURR_ADDR() bfin_read32(MDMA_D3_CURR_ADDR)
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#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR)
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#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR, val)
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#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
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#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
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#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
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@ -1642,23 +1642,23 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
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#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
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#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
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#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_read32(MDMA_S3_NEXT_DESC_PTR)
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#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR)
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#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR, val)
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#define bfin_read_MDMA_S3_START_ADDR() bfin_read32(MDMA_S3_START_ADDR)
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#define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR)
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#define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR, val)
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#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG)
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#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
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#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT)
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#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
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#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY)
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#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY)
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#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
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#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT)
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#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
|
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#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY)
|
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#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY)
|
||||
#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
|
||||
#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_read32(MDMA_S3_CURR_DESC_PTR)
|
||||
#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR)
|
||||
#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR, val)
|
||||
#define bfin_read_MDMA_S3_CURR_ADDR() bfin_read32(MDMA_S3_CURR_ADDR)
|
||||
#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR)
|
||||
#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR, val)
|
||||
#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
|
||||
#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
|
||||
#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user