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ARM: OMAP5 / DRA7: PM: Update CPU context register offset

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On OMAP5, RM_CPUi_CPUi_CONTEXT offset has changed. Update the code
so that same code works for OMAP4+ devices. DRA7 and OMAP5 have the same
context offset as well.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[rnayak@ti.com: for DRA7]
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: rebase, split/merge etc..]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
This commit is contained in:
Santosh Shilimkar 2013-02-06 19:39:07 +05:30 committed by Nishanth Menon
parent dbbe9770d1
commit a89726d3b4
1 changed files with 9 additions and 4 deletions
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13
arch/arm/mach-omap2/omap-mpuss-lowpower.c
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@ -56,6 +56,7 @@
#include "omap4-sar-layout.h" #include "omap4-sar-layout.h"
#include "pm.h" #include "pm.h"
#include "prcm_mpu44xx.h" #include "prcm_mpu44xx.h"
#include "prcm_mpu54xx.h"
#include "prminst44xx.h" #include "prminst44xx.h"
#include "prcm44xx.h" #include "prcm44xx.h"
#include "prm44xx.h" #include "prm44xx.h"
@ -89,6 +90,7 @@ struct cpu_pm_ops {
static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info); static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
static struct powerdomain *mpuss_pd; static struct powerdomain *mpuss_pd;
static void __iomem *sar_base; static void __iomem *sar_base;
static u32 cpu_context_offset;
static int default_finish_suspend(unsigned long cpu_state) static int default_finish_suspend(unsigned long cpu_state)
{ {
@ -161,14 +163,14 @@ static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id)
if (cpu_id) { if (cpu_id) {
reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST, reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST,
OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET); cpu_context_offset);
omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST, omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST,
OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET); cpu_context_offset);
} else { } else {
reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST, reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST,
OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET); cpu_context_offset);
omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST, omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST,
OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET); cpu_context_offset);
} }
} }
@ -392,6 +394,9 @@ int __init omap4_mpuss_init(void)
omap_pm_ops.finish_suspend = omap4_finish_suspend; omap_pm_ops.finish_suspend = omap4_finish_suspend;
omap_pm_ops.resume = omap4_cpu_resume; omap_pm_ops.resume = omap4_cpu_resume;
omap_pm_ops.scu_prepare = scu_pwrst_prepare; omap_pm_ops.scu_prepare = scu_pwrst_prepare;
cpu_context_offset = OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET;
} else if (soc_is_omap54xx() || soc_is_dra7xx()) {
cpu_context_offset = OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET;
} }
return 0; return 0;