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ARM: OMAP2: Fix cpu detection
At some point omap2 changed the bits for GET_OMAP_CLASS, which broke 15xx detection on 730 as noticed by Russell King. This patch fixes omap2 cpu detection to respect the original GET_OMAP_CLASS, and simplifies the detection for 34xx. Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Tony Lindgren
parent
5ba02dcab9
commit
a882314303
@ -178,9 +178,6 @@ void __init omap_check_revision(void)
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case 0x17:
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system_rev |= 0x16;
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break;
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case 0x24:
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system_rev |= 0x24;
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break;
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default:
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printk("Unknown OMAP cpu type: 0x%02x\n", cpu_type);
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}
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@ -475,7 +475,7 @@ int __init omap2_clk_init(void)
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* Update this if there are further clock changes between ES2
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* and production parts
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*/
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if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0)) {
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if (system_rev == OMAP3430_REV_ES1_0) {
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/* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
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cpu_clkflg |= CLOCK_IN_OMAP3430ES1;
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} else {
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@ -22,39 +22,6 @@
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#include <mach/control.h>
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#include <mach/cpu.h>
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static u32 class;
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static void __iomem *tap_base;
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static u16 tap_prod_id;
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#define OMAP_TAP_IDCODE 0x0204
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#define OMAP_TAP_DIE_ID_0 0x0218
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#define OMAP_TAP_DIE_ID_1 0x021C
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#define OMAP_TAP_DIE_ID_2 0x0220
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#define OMAP_TAP_DIE_ID_3 0x0224
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/* system_rev fields for OMAP2 processors:
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* CPU id bits [31:16],
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* CPU device type [15:12], (unprg,normal,POP)
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* CPU revision [11:08]
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* CPU class bits [07:00]
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*/
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struct omap_id {
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u16 hawkeye; /* Silicon type (Hawkeye id) */
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u8 dev; /* Device type from production_id reg */
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u32 type; /* combined type id copied to system_rev */
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};
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/* Register values to detect the OMAP version */
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static struct omap_id omap_ids[] __initdata = {
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{ .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200000 },
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{ .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201000 },
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{ .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202000 },
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{ .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220000 },
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{ .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230000 },
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{ .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300000 },
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};
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static struct omap_chip_id omap_chip;
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/**
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@ -70,135 +37,41 @@ int omap_chip_is(struct omap_chip_id oci)
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}
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EXPORT_SYMBOL(omap_chip_is);
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static u32 __init read_tap_reg(int reg)
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{
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unsigned int regval = 0;
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u32 cpuid;
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/*----------------------------------------------------------------------------*/
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/* Reading the IDCODE register on 3430 ES1 results in a
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* data abort as the register is not exposed on the OCP
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* Hence reading the Cortex Rev
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*/
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cpuid = read_cpuid(CPUID_ID);
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#define OMAP_TAP_IDCODE 0x0204
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#define OMAP_TAP_DIE_ID_0 0x0218
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#define OMAP_TAP_DIE_ID_1 0x021C
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#define OMAP_TAP_DIE_ID_2 0x0220
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#define OMAP_TAP_DIE_ID_3 0x0224
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/* If the processor type is Cortex-A8 and the revision is 0x0
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* it means its Cortex r0p0 which is 3430 ES1
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*/
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if ((((cpuid >> 4) & 0xFFF) == 0xC08) && ((cpuid & 0xF) == 0x0)) {
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#define read_tap_reg(reg) __raw_readl(tap_base + (reg))
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if (reg == tap_prod_id) {
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regval = 0x000F00F0;
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goto out;
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}
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struct omap_id {
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u16 hawkeye; /* Silicon type (Hawkeye id) */
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u8 dev; /* Device type from production_id reg */
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u32 type; /* Combined type id copied to system_rev */
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};
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switch (reg) {
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case OMAP_TAP_IDCODE : regval = 0x0B7AE02F; break;
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/* Making DevType as 0xF in ES1 to differ from ES2 */
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case OMAP_TAP_DIE_ID_0: regval = 0x01000000; break;
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case OMAP_TAP_DIE_ID_1: regval = 0x1012d687; break;
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case OMAP_TAP_DIE_ID_2: regval = 0x00000000; break;
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case OMAP_TAP_DIE_ID_3: regval = 0x2d2c0000; break;
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}
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} else
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regval = __raw_readl(tap_base + reg);
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/* Register values to detect the OMAP version */
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static struct omap_id omap_ids[] __initdata = {
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{ .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
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{ .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
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{ .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
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{ .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
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{ .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
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{ .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
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};
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out:
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return regval;
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}
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/*
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* _set_system_rev - set the system_rev global based on current OMAP chip type
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*
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* Set the system_rev global. This is primarily used by the cpu_is_omapxxxx()
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* macros.
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*/
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static void __init _set_system_rev(u32 type, u8 rev)
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{
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u32 i, ctrl_status;
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/*
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* system_rev encoding is as follows
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* system_rev & 0xff000000 -> Omap Class (24xx/34xx)
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* system_rev & 0xfff00000 -> Omap Sub Class (242x/343x)
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* system_rev & 0xffff0000 -> Omap type (2420/2422/2423/2430/3430)
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* system_rev & 0x0000f000 -> Silicon revision (ES1, ES2 )
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* system_rev & 0x00000700 -> Device Type ( EMU/HS/GP/BAD )
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* system_rev & 0x000000c0 -> IDCODE revision[6:7]
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* system_rev & 0x0000003f -> sys_boot[0:5]
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*/
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/* Embedding the ES revision info in type field */
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system_rev = type;
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/* Also add IDCODE revision info only two lower bits */
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system_rev |= ((rev & 0x3) << 6);
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/* Add in the device type and sys_boot fields (see above) */
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if (cpu_is_omap24xx()) {
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i = OMAP24XX_CONTROL_STATUS;
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} else if (cpu_is_omap343x()) {
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i = OMAP343X_CONTROL_STATUS;
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} else {
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printk(KERN_ERR "id: unknown CPU type\n");
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BUG();
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}
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ctrl_status = omap_ctrl_readl(i);
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system_rev |= (ctrl_status & (OMAP2_SYSBOOT_5_MASK |
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OMAP2_SYSBOOT_4_MASK |
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OMAP2_SYSBOOT_3_MASK |
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OMAP2_SYSBOOT_2_MASK |
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OMAP2_SYSBOOT_1_MASK |
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OMAP2_SYSBOOT_0_MASK));
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system_rev |= (ctrl_status & OMAP2_DEVICETYPE_MASK);
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}
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/*
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* _set_omap_chip - set the omap_chip global based on OMAP chip type
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*
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* Build the omap_chip bits. This variable is used by powerdomain and
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* clockdomain code to indicate whether structures are applicable for
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* the current OMAP chip type by ANDing it against a 'platform' bitfield
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* in the structure.
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*/
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static void __init _set_omap_chip(void)
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{
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if (cpu_is_omap343x()) {
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omap_chip.oc = CHIP_IS_OMAP3430;
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if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0))
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omap_chip.oc |= CHIP_IS_OMAP3430ES1;
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else if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0))
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omap_chip.oc |= CHIP_IS_OMAP3430ES2;
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} else if (cpu_is_omap243x()) {
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/* Currently only supports 2430ES2.1 and 2430-all */
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omap_chip.oc |= CHIP_IS_OMAP2430;
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} else if (cpu_is_omap242x()) {
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/* Currently only supports 2420ES2.1.1 and 2420-all */
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omap_chip.oc |= CHIP_IS_OMAP2420;
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} else {
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/* Current CPU not supported by this code. */
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printk(KERN_WARNING "OMAP chip type code does not yet support "
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"this CPU type.\n");
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WARN_ON(1);
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}
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}
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static void __iomem *tap_base;
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static u16 tap_prod_id;
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void __init omap24xx_check_revision(void)
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{
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int i, j;
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u32 idcode;
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u32 prod_id;
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u32 idcode, prod_id;
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u16 hawkeye;
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u8 dev_type;
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u8 rev;
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u8 dev_type, rev;
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idcode = read_tap_reg(OMAP_TAP_IDCODE);
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prod_id = read_tap_reg(tap_prod_id);
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@ -220,18 +93,6 @@ void __init omap24xx_check_revision(void)
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pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
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prod_id, dev_type);
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/*
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* Detection for 34xx ES2.0 and above can be done with just
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* hawkeye and rev. See TRM 1.5.2 Device Identification.
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* Note that rev cannot be used directly as ES1.0 uses value 0.
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*/
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if (hawkeye == 0xb7ae) {
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system_rev = 0x34300000 | ((1 + rev) << 12);
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pr_info("OMAP%04x ES2.%i\n", system_rev >> 16, rev);
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_set_omap_chip();
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return;
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}
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/* Check hawkeye ids */
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for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
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if (hawkeye == omap_ids[i].hawkeye)
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@ -255,28 +116,115 @@ void __init omap24xx_check_revision(void)
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j = i;
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}
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_set_system_rev(omap_ids[j].type, rev);
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_set_omap_chip();
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pr_info("OMAP%04x", system_rev >> 16);
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if ((system_rev >> 8) & 0x0f)
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pr_info("ES%x", (system_rev >> 12) & 0xf);
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pr_info("\n");
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}
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void __init omap34xx_check_revision(void)
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{
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u32 cpuid, idcode;
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u16 hawkeye;
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u8 rev;
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char *rev_name = "ES1.0";
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/*
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* We cannot access revision registers on ES1.0.
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* If the processor type is Cortex-A8 and the revision is 0x0
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* it means its Cortex r0p0 which is 3430 ES1.0.
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*/
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cpuid = read_cpuid(CPUID_ID);
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if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
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system_rev = OMAP3430_REV_ES1_0;
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goto out;
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}
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/*
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* Detection for 34xx ES2.0 and above can be done with just
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* hawkeye and rev. See TRM 1.5.2 Device Identification.
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* Note that rev does not map directly to our defined processor
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* revision numbers as ES1.0 uses value 0.
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*/
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idcode = read_tap_reg(OMAP_TAP_IDCODE);
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hawkeye = (idcode >> 12) & 0xffff;
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rev = (idcode >> 28) & 0xff;
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if (hawkeye == 0xb7ae) {
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switch (rev) {
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case 0:
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system_rev = OMAP3430_REV_ES2_0;
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rev_name = "ES2.0";
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break;
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case 2:
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system_rev = OMAP3430_REV_ES2_1;
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rev_name = "ES2.1";
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break;
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case 3:
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system_rev = OMAP3430_REV_ES3_0;
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rev_name = "ES3.0";
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break;
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default:
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/* Use the latest known revision as default */
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system_rev = OMAP3430_REV_ES3_0;
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rev_name = "Unknown revision\n";
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}
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}
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out:
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pr_info("OMAP%04x %s\n", system_rev >> 16, rev_name);
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}
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/*
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* Try to detect the exact revision of the omap we're running on
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*/
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void __init omap2_check_revision(void)
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{
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/*
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* At this point we have an idea about the processor revision set
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* earlier with omap2_set_globals_tap().
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*/
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if (cpu_is_omap24xx())
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omap24xx_check_revision();
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else if (cpu_is_omap34xx())
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omap34xx_check_revision();
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else
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pr_err("OMAP revision unknown, please fix!\n");
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/*
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* OK, now we know the exact revision. Initialize omap_chip bits
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* for powerdowmain and clockdomain code.
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*/
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if (cpu_is_omap243x()) {
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/* Currently only supports 2430ES2.1 and 2430-all */
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omap_chip.oc |= CHIP_IS_OMAP2430;
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} else if (cpu_is_omap242x()) {
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/* Currently only supports 2420ES2.1.1 and 2420-all */
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omap_chip.oc |= CHIP_IS_OMAP2420;
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} else if (cpu_is_omap343x()) {
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omap_chip.oc = CHIP_IS_OMAP3430;
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if (system_rev == OMAP3430_REV_ES1_0)
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omap_chip.oc |= CHIP_IS_OMAP3430ES1;
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else if (system_rev > OMAP3430_REV_ES1_0)
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omap_chip.oc |= CHIP_IS_OMAP3430ES2;
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} else {
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pr_err("Uninitialized omap_chip, please fix!\n");
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}
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}
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/*
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* Set up things for map_io and processor detection later on. Gets called
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* pretty much first thing from board init. For multi-omap, this gets
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* cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
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* detect the exact revision later on in omap2_detect_revision() once map_io
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* is done.
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*/
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void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
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{
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class = omap2_globals->class;
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system_rev = omap2_globals->class;
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tap_base = omap2_globals->tap;
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if (class == 0x3430)
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if (cpu_is_omap34xx())
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tap_prod_id = 0x0210;
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else
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tap_prod_id = 0x0208;
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@ -28,14 +28,19 @@
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struct omap_chip_id {
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u8 oc;
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u8 type;
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};
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#define OMAP_CHIP_INIT(x) { .oc = x }
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/*
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* system_rev bits:
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* CPU id bits (0730, 1510, 1710, 2422...) [31:16]
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* CPU revision (See _REV_ defined in cpu.h) [15:08]
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* CPU class bits (15xx, 16xx, 24xx, 34xx...) [07:00]
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*/
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extern unsigned int system_rev;
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#define omap2_cpu_rev() ((system_rev >> 12) & 0x0f)
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/*
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* Test if multicore OMAP support is needed
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*/
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@ -108,7 +113,7 @@ extern unsigned int system_rev;
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* cpu_is_omap243x(): True for OMAP2430
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* cpu_is_omap343x(): True for OMAP3430
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*/
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#define GET_OMAP_CLASS ((system_rev >> 24) & 0xff)
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#define GET_OMAP_CLASS (system_rev & 0xff)
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#define IS_OMAP_CLASS(class, id) \
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static inline int is_omap ##class (void) \
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@ -320,44 +325,20 @@ IS_OMAP_TYPE(3430, 0x3430)
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#define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx())
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#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
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/*
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* Macros to detect silicon revision of OMAP2/3 processors.
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* is_sil_rev_greater_than: true if passed cpu type & its rev is greater.
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* is_sil_rev_lesser_than: true if passed cpu type & its rev is lesser.
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* is_sil_rev_equal_to: true if passed cpu type & its rev is equal.
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* get_sil_rev: return the silicon rev value.
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*/
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#define get_sil_omap_type(rev) ((rev & 0xffff0000) >> 16)
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#define get_sil_revision(rev) ((rev & 0x0000f000) >> 12)
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#define is_sil_rev_greater_than(rev) \
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((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \
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(get_sil_revision(system_rev) > get_sil_revision(rev)))
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/* Various silicon revisions for omap2 */
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#define OMAP242X_CLASS 0x24200024
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#define OMAP2420_REV_ES1_0 0x24200024
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#define OMAP2420_REV_ES2_0 0x24201024
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#define is_sil_rev_less_than(rev) \
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((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \
|
||||
(get_sil_revision(system_rev) < get_sil_revision(rev)))
|
||||
#define OMAP243X_CLASS 0x24300024
|
||||
#define OMAP2430_REV_ES1_0 0x24300024
|
||||
|
||||
#define is_sil_rev_equal_to(rev) \
|
||||
((get_sil_omap_type(system_rev) == get_sil_omap_type(rev)) && \
|
||||
(get_sil_revision(system_rev) == get_sil_revision(rev)))
|
||||
|
||||
#define get_sil_rev() \
|
||||
get_sil_revision(system_rev)
|
||||
|
||||
/* Various silicon macros defined here */
|
||||
#define OMAP242X_CLASS 0x24200000
|
||||
#define OMAP2420_REV_ES1_0 0x24200000
|
||||
#define OMAP2420_REV_ES2_0 0x24201000
|
||||
|
||||
#define OMAP243X_CLASS 0x24300000
|
||||
#define OMAP2430_REV_ES1_0 0x24300000
|
||||
|
||||
#define OMAP343X_CLASS 0x34300000
|
||||
#define OMAP3430_REV_ES1_0 0x34300000
|
||||
#define OMAP3430_REV_ES2_0 0x34301000
|
||||
#define OMAP3430_REV_ES2_1 0x34302000
|
||||
#define OMAP3430_REV_ES2_2 0x34303000
|
||||
#define OMAP343X_CLASS 0x34300034
|
||||
#define OMAP3430_REV_ES1_0 0x34300034
|
||||
#define OMAP3430_REV_ES2_0 0x34301034
|
||||
#define OMAP3430_REV_ES2_1 0x34302034
|
||||
#define OMAP3430_REV_ES3_0 0x34303034
|
||||
|
||||
/*
|
||||
* omap_chip bits
|
||||
@ -382,23 +363,16 @@ IS_OMAP_TYPE(3430, 0x3430)
|
||||
#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
|
||||
|
||||
int omap_chip_is(struct omap_chip_id oci);
|
||||
|
||||
int omap_type(void);
|
||||
|
||||
/*
|
||||
* Macro to detect device type i.e. EMU/HS/TST/GP/BAD
|
||||
*/
|
||||
#define DEVICE_TYPE_TEST 0
|
||||
#define DEVICE_TYPE_EMU 1
|
||||
#define DEVICE_TYPE_SEC 2
|
||||
#define DEVICE_TYPE_GP 3
|
||||
#define DEVICE_TYPE_BAD 4
|
||||
|
||||
#define get_device_type() ((system_rev & 0x700) >> 8)
|
||||
#define is_device_type_test() (get_device_type() == DEVICE_TYPE_TEST)
|
||||
#define is_device_type_emu() (get_device_type() == DEVICE_TYPE_EMU)
|
||||
#define is_device_type_sec() (get_device_type() == DEVICE_TYPE_SEC)
|
||||
#define is_device_type_gp() (get_device_type() == DEVICE_TYPE_GP)
|
||||
#define is_device_type_bad() (get_device_type() == DEVICE_TYPE_BAD)
|
||||
#define OMAP2_DEVICE_TYPE_TEST 0
|
||||
#define OMAP2_DEVICE_TYPE_EMU 1
|
||||
#define OMAP2_DEVICE_TYPE_SEC 2
|
||||
#define OMAP2_DEVICE_TYPE_GP 3
|
||||
#define OMAP2_DEVICE_TYPE_BAD 4
|
||||
|
||||
void omap2_check_revision(void);
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user