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Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc
* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: [POWERPC] Silence an annoying boot message [POWERPC] Fix early btext debug on PowerMac [POWERPC] Demote clockevent printk to KERN_DEBUG [POWERPC] Fix CONFIG_SMP=n build error on ppc64 [POWERPC] Avoid unpaired stwcx. on some processors [POWERPC] Fix oops related to 4xx flush_tlb_page modification [POWERPC] cpm: Fix a couple minor issues in cpm_common.c. [POWERPC] Add -mno-spe for ARCH=powerpc builds
This commit is contained in:
commit
a7fe77161d
@ -107,6 +107,9 @@ endif
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# No AltiVec instruction when building kernel
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KBUILD_CFLAGS += $(call cc-option,-mno-altivec)
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# No SPE instruction when building kernel
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KBUILD_CFLAGS += $(call cc-option,-mno-spe)
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# Enable unit-at-a-time mode when possible. It shrinks the
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# kernel considerably.
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KBUILD_CFLAGS += $(call cc-option,-funit-at-a-time)
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@ -186,7 +186,9 @@ int btext_initialize(struct device_node *np)
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pitch = *prop;
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if (pitch == 1)
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pitch = 0x1000;
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prop = of_get_property(np, "address", NULL);
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prop = of_get_property(np, "linux,bootx-addr", NULL);
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if (prop == NULL)
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prop = of_get_property(np, "address", NULL);
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if (prop)
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address = *prop;
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@ -251,6 +251,9 @@ syscall_exit_cont:
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bne- 2f
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1:
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#endif /* CONFIG_44x */
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BEGIN_FTR_SECTION
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lwarx r7,0,r1
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END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
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stwcx. r0,0,r1 /* to clear the reservation */
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lwz r4,_LINK(r1)
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lwz r5,_CCR(r1)
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@ -717,6 +720,9 @@ restore:
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mtctr r11
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PPC405_ERR77(0,r1)
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BEGIN_FTR_SECTION
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lwarx r11,0,r1
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END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
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stwcx. r0,0,r1 /* to clear the reservation */
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#if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
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@ -829,7 +829,7 @@ static void register_decrementer_clockevent(int cpu)
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*dec = decrementer_clockevent;
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dec->cpumask = cpumask_of_cpu(cpu);
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printk(KERN_INFO "clockevent: %s mult[%lx] shift[%d] cpu[%d]\n",
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printk(KERN_DEBUG "clockevent: %s mult[%lx] shift[%d] cpu[%d]\n",
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dec->name, dec->mult, dec->shift, cpu);
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clockevents_register_device(dec);
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@ -19,8 +19,6 @@
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*
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*/
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#undef DEBUG
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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@ -66,12 +64,6 @@
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#include "mmu_decl.h"
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#ifdef DEBUG
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#define DBG(fmt...) printk(fmt)
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#else
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#define DBG(fmt...)
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#endif
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#if PGTABLE_RANGE > USER_VSID_RANGE
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#warning Limited user VSID range means pagetable space is wasted
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#endif
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@ -175,8 +167,8 @@ void pgtable_cache_init(void)
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int size = pgtable_cache_size[i];
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const char *name = pgtable_cache_name[i];
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DBG("Allocating page table cache %s (#%d) "
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"for size: %08x...\n", name, i, size);
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pr_debug("Allocating page table cache %s (#%d) "
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"for size: %08x...\n", name, i, size);
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pgtable_cache[i] = kmem_cache_create(name,
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size, size,
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SLAB_PANIC,
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@ -239,8 +231,8 @@ int __meminit vmemmap_populate(struct page *start_page,
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if (!p)
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return -ENOMEM;
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printk(KERN_WARNING "vmemmap %08lx allocated at %p, "
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"physical %08lx.\n", start, p, __pa(p));
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pr_debug("vmemmap %08lx allocated at %p, physical %08lx.\n",
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start, p, __pa(p));
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mapped = htab_bolt_mapping(start, start + page_size,
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__pa(p), mode_rw, mmu_linear_psize,
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@ -54,12 +54,10 @@ unsigned long pte_freelist_forced_free;
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((PAGE_SIZE - sizeof(struct pte_freelist_batch)) \
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/ sizeof(pgtable_free_t))
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#ifdef CONFIG_SMP
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static void pte_free_smp_sync(void *arg)
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{
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/* Do nothing, just ensure we sync with all CPUs */
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}
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#endif
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/* This is only called when we are critically out of memory
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* (and fail to get a page in pte_free_tlb).
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@ -77,8 +77,6 @@ int __init cpm_muram_init(void)
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int i = 0;
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int ret = 0;
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printk("cpm_muram_init\n");
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spin_lock_init(&cpm_muram_lock);
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/* initialize the info header */
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rh_init(&cpm_muram_info, 1,
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@ -193,7 +191,7 @@ void __iomem *cpm_muram_addr(unsigned long offset)
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EXPORT_SYMBOL(cpm_muram_addr);
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/**
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* cpm_muram_phys - turn a muram virtual address into a DMA address
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* cpm_muram_dma - turn a muram virtual address into a DMA address
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* @offset: virtual address from cpm_muram_addr() to convert
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*/
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dma_addr_t cpm_muram_dma(void __iomem *addr)
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@ -251,6 +251,9 @@ syscall_exit_cont:
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bne- 2f
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1:
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#endif /* CONFIG_44x */
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BEGIN_FTR_SECTION
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lwarx r7,0,r1
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END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
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stwcx. r0,0,r1 /* to clear the reservation */
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lwz r4,_LINK(r1)
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lwz r5,_CCR(r1)
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@ -713,6 +716,9 @@ restore:
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mtctr r11
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PPC405_ERR77(0,r1)
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BEGIN_FTR_SECTION
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lwarx r11,0,r1
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END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)
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stwcx. r0,0,r1 /* to clear the reservation */
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#if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE))
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@ -138,6 +138,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
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#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000)
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#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000)
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#define CPU_FTR_SPE ASM_CONST(0x0000000002000000)
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#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x0000000004000000)
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/*
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* Add the 64-bit processor unique features in the top half of the word;
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@ -261,25 +262,25 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
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#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
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CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
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CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
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CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
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CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
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#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
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CPU_FTR_USE_TB | \
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CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
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CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
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CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
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CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
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CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
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#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
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CPU_FTR_USE_TB | \
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CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
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CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
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CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
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CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
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#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
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CPU_FTR_USE_TB | \
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CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
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CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
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CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
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CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
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#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
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CPU_FTR_USE_TB | \
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CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
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CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
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CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
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CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
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@ -289,31 +290,32 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
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CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
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CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
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CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
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CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
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CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
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#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
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CPU_FTR_USE_TB | \
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CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
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CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
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CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
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CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE)
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CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
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CPU_FTR_NEED_PAIRED_STWCX)
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#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
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CPU_FTR_USE_TB | \
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CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
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CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
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CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
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CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
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CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
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#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
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CPU_FTR_USE_TB | \
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CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
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CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
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CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
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CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
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CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
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#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
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CPU_FTR_USE_TB | \
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CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
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CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
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CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
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CPU_FTR_PPC_LE)
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CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
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#define CPU_FTRS_82XX (CPU_FTR_COMMON | \
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CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
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#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
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@ -44,13 +44,13 @@ static inline void flush_tlb_mm(struct mm_struct *mm)
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static inline void flush_tlb_page(struct vm_area_struct *vma,
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unsigned long vmaddr)
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{
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_tlbie(vmaddr, vma->vm_mm->context.id);
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_tlbie(vmaddr, vma ? vma->vm_mm->context.id : 0);
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}
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static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,
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unsigned long vmaddr)
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{
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_tlbie(vmaddr, vma->vm_mm->context.id);
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_tlbie(vmaddr, vma ? vma->vm_mm->context.id : 0);
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}
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static inline void flush_tlb_range(struct vm_area_struct *vma,
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