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ARM: tegra: Core changes for v5.8-rc1

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This contains core changes needed for the CPU frequency scaling and CPU
 idle drivers on Tegra20 and Tegra30.
 -----BEGIN PGP SIGNATURE-----
 
 iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAl6+pNMTHHRyZWRpbmdA
 bnZpZGlhLmNvbQAKCRDdI6zXfz6zoYq9EACR0PciY3lTiQdmNqUGqEXp044Fg9CE
 CpnjcyJh9a+3wzwtx8ZjEng7KhwUyj3trKW6gpazjaNFTzNgOqVoYEZIetOJIc5u
 ZHFF7OYr+ZO5xmy4jYRuj6ZHSznn7ImrLLL8JVuYQHFHgxTlM1enSCRG3HN7Z2c7
 MUmM9wnio0amREKZXgnSkN87OO1r8kaKqWFUjwqs6K8j5NvTGVYW+5YIf4Zlc7PB
 5yKTt2EdPx1LpoVA+b8K/sRe8rNDwC4vxuVoDpXzBvM0s2kMIy+tIEx1plQLwkDV
 dHSMT8sk6XD9yVAuzEqai341w5dm02GTfKvSy/gLoZ2NTshF99CnpLaUd3aicq/n
 /9lkRtxYtb8uvlB+vKlv/LaUsDqA6casXXKstpGTUD5Oc2pSsXNGGTBhGfqwNO+v
 VLNPNYLDKZbXx4HEhn7vH0c43WXTD8ydxa91HZf1GcL6hcrnklI/rbnX7QCKuVzc
 IsYZPfQ1YclvaoC4wRMBhR5Hj3AW7l3N2k5oTPD+F8cIfxF5e+eELYdGOvs27ncM
 SnaNve9x1IOAZmCKEQhxQorjT1nDSDd7quasXQ9nzx7bTgIa7H+QsFOYkrIPLNHi
 ld7TpnK6/M4b6gaXqb6rvWnYKHTfNuP59843AUQafpnWhYHZJvrjg6n6XJNUe5g6
 bvXlQIbx/fhfdQ==
 =7XEQ
 -----END PGP SIGNATURE-----

Merge tag 'tegra-for-5.8-arm-core' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/soc

ARM: tegra: Core changes for v5.8-rc1

This contains core changes needed for the CPU frequency scaling and CPU
idle drivers on Tegra20 and Tegra30.

* tag 'tegra-for-5.8-arm-core' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  ARM: tegra: Create tegra20-cpufreq platform device on Tegra30
  ARM: tegra: Don't enable PLLX while resuming from LP1 on Tegra30
  ARM: tegra: Switch CPU to PLLP on resume from LP1 on Tegra30/114/124
  ARM: tegra: Correct PL310 Auxiliary Control Register initialization
  ARM: tegra: Do not fully reinitialize L2 on resume
  ARM: tegra: Initialize r0 register for firmware wake-up
  firmware: tf: Different way of L2 cache enabling after LP2 suspend
  firmware: tegra: Make BPMP a regular driver

Link: https://lore.kernel.org/r/20200515145311.1580134-10-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2020-05-15 23:12:28 +02:00
commit a7f6e07724
7 changed files with 48 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/mach-tegra/pm.c
View File

@ -216,6 +216,8 @@ int tegra_pm_enter_lp2(void)
restore_cpu_complex();
cpu_cluster_pm_exit();
call_firmware_op(prepare_idle, TF_PM_MODE_NONE);
return err;
}
@ -391,6 +393,8 @@ static int tegra_suspend_enter(suspend_state_t state)
local_fiq_enable();
call_firmware_op(prepare_idle, TF_PM_MODE_NONE);
return 0;
}

7
arch/arm/mach-tegra/reset-handler.S
View File

@ -98,7 +98,12 @@ ENTRY(tegra_resume_trusted_foundations)
reteq lr
.arch_extension sec
/* First call after suspend wakes firmware. No arguments required. */
/*
* First call after suspend wakes firmware. No arguments required
* for some firmware versions. Downstream kernel of ASUS TF300T uses
* r0=3 for the wake-up notification.
*/
mov r0, #3
smc #0
b cpu_resume

16
arch/arm/mach-tegra/sleep-tegra30.S
View File

@ -361,7 +361,6 @@ _no_pll_iddq_exit:
pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC
pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC
pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC
_pll_m_c_x_done:
pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC
@ -371,12 +370,18 @@ _pll_m_c_x_done:
pll_locked r1, r0, CLK_RESET_PLLP_BASE
pll_locked r1, r0, CLK_RESET_PLLA_BASE
pll_locked r1, r0, CLK_RESET_PLLC_BASE
pll_locked r1, r0, CLK_RESET_PLLX_BASE
/*
* CPUFreq driver could select other PLL for CPU. PLLX will be
* enabled by the Tegra30 CLK driver on an as-needed basis, see
* tegra30_cpu_clock_resume().
*/
tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
cmp r1, #TEGRA30
beq 1f
pll_locked r1, r0, CLK_RESET_PLLX_BASE
ldr r1, [r0, #CLK_RESET_PLLP_BASE]
bic r1, r1, #(1<<31) @ disable PllP bypass
str r1, [r0, #CLK_RESET_PLLP_BASE]
@ -398,11 +403,8 @@ _pll_m_c_x_done:
ldr r4, [r5, #0x1C] @ restore SCLK_BURST
str r4, [r0, #CLK_RESET_SCLK_BURST]
cmp r10, #TEGRA30
movweq r4, #:lower16:((1 << 28) | (0x8)) @ burst policy is PLLX
movteq r4, #:upper16:((1 << 28) | (0x8))
movwne r4, #:lower16:((1 << 28) | (0xe))
movtne r4, #:upper16:((1 << 28) | (0xe))
movw r4, #:lower16:((1 << 28) | (0x4)) @ burst policy is PLLP
movt r4, #:upper16:((1 << 28) | (0x4))
str r4, [r0, #CLK_RESET_CCLK_BURST]
/* Restore pad power state to normal */

8
arch/arm/mach-tegra/tegra.c
View File

@ -96,6 +96,10 @@ static void __init tegra_dt_init_late(void)
if (IS_ENABLED(CONFIG_ARM_TEGRA_CPUIDLE) && !psci_smp_available())
platform_device_register_simple("tegra-cpuidle", -1, NULL, 0);
if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) &&
of_machine_is_compatible("nvidia,tegra30"))
platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0);
}
static const char * const tegra_dt_board_compat[] = {
@ -107,8 +111,8 @@ static const char * const tegra_dt_board_compat[] = {
};
DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)")
.l2c_aux_val = 0x3c400001,
.l2c_aux_mask = 0xc20fc3fe,
.l2c_aux_val = 0x3c400000,
.l2c_aux_mask = 0xc20fc3ff,
.smp = smp_ops(tegra_smp_ops),
.map_io = tegra_map_common_io,
.init_early = tegra_init_early,

9
drivers/firmware/tegra/bpmp.c
View File

@ -6,6 +6,7 @@
#include <linux/clk/tegra.h>
#include <linux/genalloc.h>
#include <linux/mailbox_client.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
@ -869,12 +870,8 @@ static struct platform_driver tegra_bpmp_driver = {
.name = "tegra-bpmp",
.of_match_table = tegra_bpmp_match,
.pm = &tegra_bpmp_pm_ops,
.suppress_bind_attrs = true,
},
.probe = tegra_bpmp_probe,
};
static int __init tegra_bpmp_init(void)
{
return platform_driver_register(&tegra_bpmp_driver);
}
core_initcall(tegra_bpmp_init);
builtin_platform_driver(tegra_bpmp_driver);

21
drivers/firmware/trusted_foundations.c
View File

@ -19,6 +19,7 @@
#define TF_CACHE_ENABLE 1
#define TF_CACHE_DISABLE 2
#define TF_CACHE_REENABLE 4
#define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200
@ -29,6 +30,7 @@
#define TF_CPU_PM_S1 0xffffffe4
#define TF_CPU_PM_S1_NOFLUSH_L2 0xffffffe7
static unsigned long tf_idle_mode = TF_PM_MODE_NONE;
static unsigned long cpu_boot_addr;
static void tf_generic_smc(u32 type, u32 arg1, u32 arg2)
@ -85,25 +87,40 @@ static int tf_prepare_idle(unsigned long mode)
cpu_boot_addr);
break;
case TF_PM_MODE_NONE:
break;
default:
return -EINVAL;
}
tf_idle_mode = mode;
return 0;
}
#ifdef CONFIG_CACHE_L2X0
static void tf_cache_write_sec(unsigned long val, unsigned int reg)
{
u32 l2x0_way_mask = 0xff;
u32 enable_op, l2x0_way_mask = 0xff;
switch (reg) {
case L2X0_CTRL:
if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_ASSOCIATIVITY_16)
l2x0_way_mask = 0xffff;
switch (tf_idle_mode) {
case TF_PM_MODE_LP2:
enable_op = TF_CACHE_REENABLE;
break;
default:
enable_op = TF_CACHE_ENABLE;
break;
}
if (val == L2X0_CTRL_EN)
tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_ENABLE,
tf_generic_smc(TF_CACHE_MAINT, enable_op,
l2x0_saved_regs.aux_ctrl);
else
tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_DISABLE,

1
include/linux/firmware/trusted_foundations.h
View File

@ -32,6 +32,7 @@
#define TF_PM_MODE_LP1_NO_MC_CLK 2
#define TF_PM_MODE_LP2 3
#define TF_PM_MODE_LP2_NOFLUSH_L2 4
#define TF_PM_MODE_NONE 5
struct trusted_foundations_platform_data {
unsigned int version_major;