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dt-bindings: ata: convert MediaTek controller to the json-schema
This helps validating DTS files. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Niklas Cassel <cassel@kernel.org>
This commit is contained in:
Rafał Miłecki
Niklas Cassel
parent
8731215112
commit
a783b2af74
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MediaTek Serial ATA controller
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Required properties:
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- compatible : Must be "mediatek,<chip>-ahci", "mediatek,mtk-ahci".
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When using "mediatek,mtk-ahci" compatible strings, you
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need SoC specific ones in addition, one of:
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- "mediatek,mt7622-ahci"
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- reg : Physical base addresses and length of register sets.
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- interrupts : Interrupt associated with the SATA device.
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- interrupt-names : Associated name must be: "hostc".
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- clocks : A list of phandle and clock specifier pairs, one for each
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entry in clock-names.
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- clock-names : Associated names must be: "ahb", "axi", "asic", "rbc", "pm".
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- phys : A phandle and PHY specifier pair for the PHY port.
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- phy-names : Associated name must be: "sata-phy".
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- ports-implemented : See ./ahci-platform.txt for details.
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Optional properties:
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- power-domains : A phandle and power domain specifier pair to the power
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domain which is responsible for collapsing and restoring
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power to the peripheral.
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- resets : Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names : Associated names must be: "axi", "sw", "reg".
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- mediatek,phy-mode : A phandle to the system controller, used to enable
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SATA function.
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Example:
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sata: sata@1a200000 {
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compatible = "mediatek,mt7622-ahci",
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"mediatek,mtk-ahci";
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reg = <0 0x1a200000 0 0x1100>;
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interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hostc";
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clocks = <&pciesys CLK_SATA_AHB_EN>,
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<&pciesys CLK_SATA_AXI_EN>,
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<&pciesys CLK_SATA_ASIC_EN>,
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<&pciesys CLK_SATA_RBC_EN>,
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<&pciesys CLK_SATA_PM_EN>;
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clock-names = "ahb", "axi", "asic", "rbc", "pm";
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phys = <&u3port1 PHY_TYPE_SATA>;
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phy-names = "sata-phy";
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ports-implemented = <0x1>;
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power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
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resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
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<&pciesys MT7622_SATA_PHY_SW_RST>,
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<&pciesys MT7622_SATA_PHY_REG_RST>;
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reset-names = "axi", "sw", "reg";
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mediatek,phy-mode = <&pciesys>;
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};
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98
Documentation/devicetree/bindings/ata/mediatek,mtk-ahci.yaml
Normal file
98
Documentation/devicetree/bindings/ata/mediatek,mtk-ahci.yaml
Normal file
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/ata/mediatek,mtk-ahci.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek Serial ATA controller
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maintainers:
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- Ryder Lee <ryder.lee@mediatek.com>
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allOf:
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- $ref: ahci-common.yaml#
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properties:
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compatible:
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items:
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- enum:
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- mediatek,mt7622-ahci
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- const: mediatek,mtk-ahci
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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interrupt-names:
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const: hostc
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clocks:
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maxItems: 5
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clock-names:
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items:
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- const: ahb
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- const: axi
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- const: asic
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- const: rbc
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- const: pm
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power-domains:
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maxItems: 1
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resets:
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maxItems: 3
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reset-names:
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items:
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- const: axi
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- const: sw
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- const: reg
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mediatek,phy-mode:
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description: System controller phandle, used to enable SATA function
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$ref: /schemas/types.yaml#/definitions/phandle
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required:
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- reg
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- interrupts
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- interrupt-names
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- clocks
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- clock-names
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- phys
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- phy-names
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- ports-implemented
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mt7622-clk.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/power/mt7622-power.h>
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#include <dt-bindings/reset/mt7622-reset.h>
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sata@1a200000 {
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compatible = "mediatek,mt7622-ahci", "mediatek,mtk-ahci";
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reg = <0x1a200000 0x1100>;
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interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hostc";
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clocks = <&pciesys CLK_SATA_AHB_EN>,
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<&pciesys CLK_SATA_AXI_EN>,
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<&pciesys CLK_SATA_ASIC_EN>,
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<&pciesys CLK_SATA_RBC_EN>,
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<&pciesys CLK_SATA_PM_EN>;
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clock-names = "ahb", "axi", "asic", "rbc", "pm";
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phys = <&u3port1 PHY_TYPE_SATA>;
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phy-names = "sata-phy";
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ports-implemented = <0x1>;
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power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
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resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
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<&pciesys MT7622_SATA_PHY_SW_RST>,
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<&pciesys MT7622_SATA_PHY_REG_RST>;
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reset-names = "axi", "sw", "reg";
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mediatek,phy-mode = <&pciesys>;
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};
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