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NET: sa11x0-ir: move SIR and FIR interrupt support
Move the interrupt handlers to the SIR and FIR sections of the file. This improves the localization of the protocol handlers. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King
parent
374f77390c
commit
a6b2ea66d6
@ -164,6 +164,100 @@ static int sa1100_irda_sir_tx_start(struct sk_buff *skb, struct net_device *dev,
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return NETDEV_TX_OK;
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}
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static irqreturn_t sa1100_irda_sir_irq(struct net_device *dev, struct sa1100_irda *si)
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{
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int status;
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status = Ser2UTSR0;
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/*
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* Deal with any receive errors first. The bytes in error may be
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* the only bytes in the receive FIFO, so we do this first.
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*/
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while (status & UTSR0_EIF) {
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int stat, data;
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stat = Ser2UTSR1;
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data = Ser2UTDR;
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if (stat & (UTSR1_FRE | UTSR1_ROR)) {
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dev->stats.rx_errors++;
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if (stat & UTSR1_FRE)
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dev->stats.rx_frame_errors++;
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if (stat & UTSR1_ROR)
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dev->stats.rx_fifo_errors++;
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} else
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async_unwrap_char(dev, &dev->stats, &si->rx_buff, data);
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status = Ser2UTSR0;
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}
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/*
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* We must clear certain bits.
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*/
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Ser2UTSR0 = status & (UTSR0_RID | UTSR0_RBB | UTSR0_REB);
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if (status & UTSR0_RFS) {
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/*
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* There are at least 4 bytes in the FIFO. Read 3 bytes
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* and leave the rest to the block below.
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*/
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async_unwrap_char(dev, &dev->stats, &si->rx_buff, Ser2UTDR);
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async_unwrap_char(dev, &dev->stats, &si->rx_buff, Ser2UTDR);
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async_unwrap_char(dev, &dev->stats, &si->rx_buff, Ser2UTDR);
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}
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if (status & (UTSR0_RFS | UTSR0_RID)) {
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/*
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* Fifo contains more than 1 character.
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*/
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do {
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async_unwrap_char(dev, &dev->stats, &si->rx_buff,
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Ser2UTDR);
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} while (Ser2UTSR1 & UTSR1_RNE);
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}
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if (status & UTSR0_TFS && si->tx_buff.len) {
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/*
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* Transmitter FIFO is not full
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*/
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do {
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Ser2UTDR = *si->tx_buff.data++;
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si->tx_buff.len -= 1;
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} while (Ser2UTSR1 & UTSR1_TNF && si->tx_buff.len);
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if (si->tx_buff.len == 0) {
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dev->stats.tx_packets++;
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dev->stats.tx_bytes += si->tx_buff.data -
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si->tx_buff.head;
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/*
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* We need to ensure that the transmitter has
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* finished.
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*/
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do
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rmb();
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while (Ser2UTSR1 & UTSR1_TBY);
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/*
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* Ok, we've finished transmitting. Now enable
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* the receiver. Sometimes we get a receive IRQ
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* immediately after a transmit...
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*/
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Ser2UTSR0 = UTSR0_REB | UTSR0_RBB | UTSR0_RID;
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Ser2UTCR3 = UTCR3_RIE | UTCR3_RXE | UTCR3_TXE;
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sa1100_irda_check_speed(si);
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/* I'm hungry! */
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netif_wake_queue(dev);
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}
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}
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return IRQ_HANDLED;
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}
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/*
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* FIR format support.
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*/
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@ -198,8 +292,128 @@ static int sa1100_irda_fir_tx_start(struct sk_buff *skb, struct net_device *dev,
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return NETDEV_TX_OK;
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}
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static irqreturn_t sa1100_irda_sir_irq(struct net_device *, struct sa1100_irda *);
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static irqreturn_t sa1100_irda_fir_irq(struct net_device *, struct sa1100_irda *);
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static void sa1100_irda_fir_error(struct sa1100_irda *si, struct net_device *dev)
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{
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struct sk_buff *skb = si->dma_rx.skb;
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dma_addr_t dma_addr;
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unsigned int len, stat, data;
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if (!skb) {
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printk(KERN_ERR "sa1100_ir: SKB is NULL!\n");
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return;
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}
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/*
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* Get the current data position.
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*/
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dma_addr = sa1100_get_dma_pos(si->dma_rx.regs);
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len = dma_addr - si->dma_rx.dma;
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if (len > HPSIR_MAX_RXLEN)
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len = HPSIR_MAX_RXLEN;
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dma_unmap_single(si->dev, si->dma_rx.dma, len, DMA_FROM_DEVICE);
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do {
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/*
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* Read Status, and then Data.
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*/
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stat = Ser2HSSR1;
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rmb();
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data = Ser2HSDR;
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if (stat & (HSSR1_CRE | HSSR1_ROR)) {
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dev->stats.rx_errors++;
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if (stat & HSSR1_CRE)
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dev->stats.rx_crc_errors++;
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if (stat & HSSR1_ROR)
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dev->stats.rx_frame_errors++;
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} else
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skb->data[len++] = data;
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/*
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* If we hit the end of frame, there's
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* no point in continuing.
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*/
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if (stat & HSSR1_EOF)
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break;
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} while (Ser2HSSR0 & HSSR0_EIF);
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if (stat & HSSR1_EOF) {
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si->dma_rx.skb = NULL;
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skb_put(skb, len);
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skb->dev = dev;
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skb_reset_mac_header(skb);
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skb->protocol = htons(ETH_P_IRDA);
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dev->stats.rx_packets++;
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dev->stats.rx_bytes += len;
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/*
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* Before we pass the buffer up, allocate a new one.
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*/
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sa1100_irda_rx_alloc(si);
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netif_rx(skb);
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} else {
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/*
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* Remap the buffer - it was previously mapped, and we
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* hope that this succeeds.
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*/
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si->dma_rx.dma = dma_map_single(si->dev, si->dma_rx.skb->data,
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HPSIR_MAX_RXLEN,
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DMA_FROM_DEVICE);
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}
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}
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/*
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* We only have to handle RX events here; transmit events go via the TX
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* DMA handler. We disable RX, process, and the restart RX.
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*/
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static irqreturn_t sa1100_irda_fir_irq(struct net_device *dev, struct sa1100_irda *si)
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{
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/*
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* Stop RX DMA
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*/
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sa1100_stop_dma(si->dma_rx.regs);
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/*
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* Framing error - we throw away the packet completely.
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* Clearing RXE flushes the error conditions and data
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* from the fifo.
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*/
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if (Ser2HSSR0 & (HSSR0_FRE | HSSR0_RAB)) {
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dev->stats.rx_errors++;
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if (Ser2HSSR0 & HSSR0_FRE)
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dev->stats.rx_frame_errors++;
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/*
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* Clear out the DMA...
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*/
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Ser2HSCR0 = si->hscr0 | HSCR0_HSSP;
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/*
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* Clear selected status bits now, so we
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* don't miss them next time around.
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*/
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Ser2HSSR0 = HSSR0_FRE | HSSR0_RAB;
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}
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/*
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* Deal with any receive errors. The any of the lowest
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* 8 bytes in the FIFO may contain an error. We must read
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* them one by one. The "error" could even be the end of
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* packet!
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*/
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if (Ser2HSSR0 & HSSR0_EIF)
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sa1100_irda_fir_error(si, dev);
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/*
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* No matter what happens, we must restart reception.
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*/
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sa1100_irda_rx_dma_start(si);
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return IRQ_HANDLED;
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}
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/*
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* Set the IrDA communications speed.
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@ -306,228 +520,6 @@ sa1100_set_power(struct sa1100_irda *si, unsigned int state)
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return ret;
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}
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/*
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* HP-SIR format interrupt service routines.
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*/
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static irqreturn_t sa1100_irda_sir_irq(struct net_device *dev, struct sa1100_irda *si)
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{
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int status;
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status = Ser2UTSR0;
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/*
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* Deal with any receive errors first. The bytes in error may be
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* the only bytes in the receive FIFO, so we do this first.
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*/
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while (status & UTSR0_EIF) {
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int stat, data;
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stat = Ser2UTSR1;
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data = Ser2UTDR;
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if (stat & (UTSR1_FRE | UTSR1_ROR)) {
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dev->stats.rx_errors++;
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if (stat & UTSR1_FRE)
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dev->stats.rx_frame_errors++;
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if (stat & UTSR1_ROR)
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dev->stats.rx_fifo_errors++;
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} else
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async_unwrap_char(dev, &dev->stats, &si->rx_buff, data);
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status = Ser2UTSR0;
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}
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/*
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* We must clear certain bits.
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*/
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Ser2UTSR0 = status & (UTSR0_RID | UTSR0_RBB | UTSR0_REB);
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if (status & UTSR0_RFS) {
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/*
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* There are at least 4 bytes in the FIFO. Read 3 bytes
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* and leave the rest to the block below.
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*/
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async_unwrap_char(dev, &dev->stats, &si->rx_buff, Ser2UTDR);
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async_unwrap_char(dev, &dev->stats, &si->rx_buff, Ser2UTDR);
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async_unwrap_char(dev, &dev->stats, &si->rx_buff, Ser2UTDR);
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}
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if (status & (UTSR0_RFS | UTSR0_RID)) {
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/*
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* Fifo contains more than 1 character.
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*/
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do {
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async_unwrap_char(dev, &dev->stats, &si->rx_buff,
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Ser2UTDR);
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} while (Ser2UTSR1 & UTSR1_RNE);
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}
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if (status & UTSR0_TFS && si->tx_buff.len) {
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/*
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* Transmitter FIFO is not full
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*/
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do {
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Ser2UTDR = *si->tx_buff.data++;
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si->tx_buff.len -= 1;
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} while (Ser2UTSR1 & UTSR1_TNF && si->tx_buff.len);
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if (si->tx_buff.len == 0) {
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dev->stats.tx_packets++;
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dev->stats.tx_bytes += si->tx_buff.data -
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si->tx_buff.head;
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/*
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* We need to ensure that the transmitter has
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* finished.
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*/
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do
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rmb();
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while (Ser2UTSR1 & UTSR1_TBY);
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/*
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* Ok, we've finished transmitting. Now enable
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* the receiver. Sometimes we get a receive IRQ
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* immediately after a transmit...
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*/
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Ser2UTSR0 = UTSR0_REB | UTSR0_RBB | UTSR0_RID;
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Ser2UTCR3 = UTCR3_RIE | UTCR3_RXE | UTCR3_TXE;
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sa1100_irda_check_speed(si);
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/* I'm hungry! */
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netif_wake_queue(dev);
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}
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}
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return IRQ_HANDLED;
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}
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static void sa1100_irda_fir_error(struct sa1100_irda *si, struct net_device *dev)
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{
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struct sk_buff *skb = si->dma_rx.skb;
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dma_addr_t dma_addr;
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unsigned int len, stat, data;
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if (!skb) {
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printk(KERN_ERR "sa1100_ir: SKB is NULL!\n");
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return;
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}
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/*
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* Get the current data position.
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*/
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dma_addr = sa1100_get_dma_pos(si->dma_rx.regs);
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len = dma_addr - si->dma_rx.dma;
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if (len > HPSIR_MAX_RXLEN)
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len = HPSIR_MAX_RXLEN;
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dma_unmap_single(si->dev, si->dma_rx.dma, len, DMA_FROM_DEVICE);
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do {
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/*
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* Read Status, and then Data.
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*/
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stat = Ser2HSSR1;
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rmb();
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data = Ser2HSDR;
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if (stat & (HSSR1_CRE | HSSR1_ROR)) {
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dev->stats.rx_errors++;
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if (stat & HSSR1_CRE)
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dev->stats.rx_crc_errors++;
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if (stat & HSSR1_ROR)
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dev->stats.rx_frame_errors++;
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} else
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skb->data[len++] = data;
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/*
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* If we hit the end of frame, there's
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* no point in continuing.
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*/
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if (stat & HSSR1_EOF)
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break;
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} while (Ser2HSSR0 & HSSR0_EIF);
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if (stat & HSSR1_EOF) {
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si->dma_rx.skb = NULL;
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skb_put(skb, len);
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skb->dev = dev;
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skb_reset_mac_header(skb);
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skb->protocol = htons(ETH_P_IRDA);
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dev->stats.rx_packets++;
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dev->stats.rx_bytes += len;
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/*
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* Before we pass the buffer up, allocate a new one.
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*/
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sa1100_irda_rx_alloc(si);
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netif_rx(skb);
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} else {
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/*
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* Remap the buffer - it was previously mapped, and we
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* hope that this succeeds.
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*/
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si->dma_rx.dma = dma_map_single(si->dev, si->dma_rx.skb->data,
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HPSIR_MAX_RXLEN,
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DMA_FROM_DEVICE);
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}
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}
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/*
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* FIR format interrupt service routine. We only have to
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* handle RX events; transmit events go via the TX DMA handler.
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*
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* No matter what, we disable RX, process, and the restart RX.
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*/
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static irqreturn_t sa1100_irda_fir_irq(struct net_device *dev, struct sa1100_irda *si)
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{
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/*
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* Stop RX DMA
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*/
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sa1100_stop_dma(si->dma_rx.regs);
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/*
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* Framing error - we throw away the packet completely.
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* Clearing RXE flushes the error conditions and data
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* from the fifo.
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*/
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if (Ser2HSSR0 & (HSSR0_FRE | HSSR0_RAB)) {
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dev->stats.rx_errors++;
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if (Ser2HSSR0 & HSSR0_FRE)
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dev->stats.rx_frame_errors++;
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/*
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* Clear out the DMA...
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*/
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Ser2HSCR0 = si->hscr0 | HSCR0_HSSP;
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/*
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* Clear selected status bits now, so we
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* don't miss them next time around.
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*/
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Ser2HSSR0 = HSSR0_FRE | HSSR0_RAB;
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}
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/*
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* Deal with any receive errors. The any of the lowest
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* 8 bytes in the FIFO may contain an error. We must read
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* them one by one. The "error" could even be the end of
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* packet!
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*/
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if (Ser2HSSR0 & HSSR0_EIF)
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sa1100_irda_fir_error(si, dev);
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/*
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* No matter what happens, we must restart reception.
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*/
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sa1100_irda_rx_dma_start(si);
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return IRQ_HANDLED;
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}
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static irqreturn_t sa1100_irda_irq(int irq, void *dev_id)
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{
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struct net_device *dev = dev_id;
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