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Second Round of Renesas ARM Based SoC DT Updates for v4.9

Browse Source 
Fixes (for v4.9):
 * Correct PWM clock parent on r8a7794 SoC
 
 Clean-up:
 * Remove obsolete vsp1 properties from r8a779[01] SoCs
 
 New boards:
 * Add r8a7792/wheat and r7s72100/rskrza1 boards
 
 Enablement:
 * Enable LEDs, DU, SDHI on r8a7792/blanche board
 * Enable MMCIF and SDHI on r8a7794/alt board
 * Add SPI and VSP1 to r8a7792 SoC
 * Add ethernet to r7s72100 SoC
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Merge tag 'renesas-dt2-for-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Pull "Second Round of Renesas ARM Based SoC DT Updates for v4.9" from Simon Horman:

Fixes (for v4.9):
* Correct PWM clock parent on r8a7794 SoC

Clean-up:
* Remove obsolete vsp1 properties from r8a779[01] SoCs

New boards:
* Add r8a7792/wheat and r7s72100/rskrza1 boards

Enablement:
* Enable LEDs, DU, SDHI on r8a7792/blanche board
* Enable MMCIF and SDHI on r8a7794/alt board
* Add SPI and VSP1 to r8a7792 SoC
* Add ethernet to r7s72100 SoC

* tag 'renesas-dt2-for-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (26 commits)
  ARM: dts: wheat: add support for tactile switches
  ARM: dts: wheat: add QSPI support
  ARM: dts: r8a7792: add QSPI support
  ARM: dts: r8a7792: add QSPI clock
  ARM: dts: wheat: add SDHI0 support
  ARM: dts: wheat: add CAN support
  ARM: dts: r8a7794: fix PWM clock parent
  ARM: dts: rskrza1: add ethernet DT support
  ARM: dts: r7s72100: add ethernet to device tree
  ARM: dts: r7s72100: add ethernet clock to device tree
  ARM: dts: rskrza1: initial device tree
  ARM: dts: Add RSKRZA1 DT bindings documentation
  ARM: dts: wheat: add Ethernet support
  ARM: dts: wheat: initial device tree
  ARM: dts: document Wheat board
  ARM: dts: blanche: add support for general purpose LEDs
  ARM: dts: r8a7792: add VSP1V support
  ARM: dts: r8a7792: add VSP1V clocks
  ARM: dts: blanche: add DU support
  ARM: dts: blanche: add SDHI0 support
  ...
This commit is contained in:
Arnd Bergmann 2016-09-13 17:34:49 +02:00
commit a6023d0500
12 changed files with 683 additions and 47 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Documentation/devicetree/bindings/arm/shmobile.txt
View File

@ -63,9 +63,13 @@ Boards:
compatible = "renesas,marzen", "renesas,r8a7779"
- Porter (M2-LCDP)
compatible = "renesas,porter", "renesas,r8a7791"
- RSKRZA1 (YR0K77210C000BE)
compatible = "renesas,rskrza1", "renesas,r7s72100"
- Salvator-X (RTP0RC7795SIPB0010S)
compatible = "renesas,salvator-x", "renesas,r8a7795";
- Salvator-X
compatible = "renesas,salvator-x", "renesas,r8a7796";
- SILK (RTP0RC7794LCB00011S)
compatible = "renesas,silk", "renesas,r8a7794"
- Wheat
compatible = "renesas,wheat", "renesas,r8a7792"

2
arch/arm/boot/dts/Makefile
View File

@ -652,6 +652,7 @@ dtb-$(CONFIG_ARCH_S5PV210) += \
dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
emev2-kzm9d.dtb \
r7s72100-genmai.dtb \
r7s72100-rskrza1.dtb \
r8a73a4-ape6evm.dtb \
r8a7740-armadillo800eva.dtb \
r8a7778-bockw.dtb \
@ -660,6 +661,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
r8a7791-koelsch.dtb \
r8a7791-porter.dtb \
r8a7792-blanche.dtb \
r8a7792-wheat.dtb \
r8a7793-gose.dtb \
r8a7794-alt.dtb \
r8a7794-silk.dtb \

61
arch/arm/boot/dts/r7s72100-rskrza1.dts Normal file
View File

@ -0,0 +1,61 @@
/*
* Device Tree Source for the RZ/A1H RSK board
*
* Copyright (C) 2016 Renesas Electronics
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/dts-v1/;
#include "r7s72100.dtsi"
/ {
model = "RSKRZA1";
compatible = "renesas,rskrza1", "renesas,r7s72100";
aliases {
serial0 = &scif2;
};
chosen {
bootargs = "ignore_loglevel";
stdout-path = "serial0:115200n8";
};
memory@8000000 {
device_type = "memory";
reg = <0x08000000 0x02000000>;
};
lbsc {
#address-cells = <1>;
#size-cells = <1>;
};
};
&extal_clk {
clock-frequency = <13330000>;
};
&usb_x1_clk {
clock-frequency = <48000000>;
};
&mtu2 {
status = "okay";
};
&ether {
status = "okay";
renesas,no-ether-link;
phy-handle = <&phy0>;
phy0: ethernet-phy@0 {
reg = <0>;
};
};
&scif2 {
status = "okay";
};

22
arch/arm/boot/dts/r7s72100.dtsi
View File

@ -108,6 +108,15 @@
clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
};
mstp7_clks: mstp7_clks@fcfe0430 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0xfcfe0430 4>;
clocks = <&p0_clk>;
clock-indices = <R7S72100_CLK_ETHER>;
clock-output-names = "ether";
};
mstp9_clks: mstp9_clks@fcfe0438 {
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
@ -419,4 +428,17 @@
power-domains = <&cpg_clocks>;
status = "disabled";
};
ether: ethernet@e8203000 {
compatible = "renesas,ether-r7s72100";
reg = <0xe8203000 0x800>,
<0xe8204800 0x200>;
interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
power-domains = <&cpg_clocks>;
phy-mode = "mii";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};

23
arch/arm/boot/dts/r8a7790.dtsi
View File

@ -944,11 +944,6 @@
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
renesas,has-sru;
renesas,#rpf = <5>;
renesas,#uds = <1>;
renesas,#wpf = <4>;
};
vsp1@fe928000 {
@ -957,12 +952,6 @@
interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
renesas,has-lut;
renesas,has-sru;
renesas,#rpf = <5>;
renesas,#uds = <3>;
renesas,#wpf = <4>;
};
vsp1@fe930000 {
@ -971,12 +960,6 @@
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
renesas,has-lif;
renesas,has-lut;
renesas,#rpf = <4>;
renesas,#uds = <1>;
renesas,#wpf = <4>;
};
vsp1@fe938000 {
@ -985,12 +968,6 @@
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
renesas,has-lif;
renesas,has-lut;
renesas,#rpf = <4>;
renesas,#uds = <1>;
renesas,#wpf = <4>;
};
du: display@feb00000 {

18
arch/arm/boot/dts/r8a7791.dtsi
View File

@ -983,12 +983,6 @@
interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
renesas,has-lut;
renesas,has-sru;
renesas,#rpf = <5>;
renesas,#uds = <3>;
renesas,#wpf = <4>;
};
vsp1@fe930000 {
@ -997,12 +991,6 @@
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
renesas,has-lif;
renesas,has-lut;
renesas,#rpf = <4>;
renesas,#uds = <1>;
renesas,#wpf = <4>;
};
vsp1@fe938000 {
@ -1011,12 +999,6 @@
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>;
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
renesas,has-lif;
renesas,has-lut;
renesas,#rpf = <4>;
renesas,#uds = <1>;
renesas,#wpf = <4>;
};
du: display@feb00000 {

216
arch/arm/boot/dts/r8a7792-blanche.dts
View File

@ -11,6 +11,8 @@
/dts-v1/;
#include "r8a7792.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Blanche";
@ -54,6 +56,136 @@
pinctrl-0 = <&lan89218_pins>;
pinctrl-names = "default";
};
vga-encoder {
compatible = "adi,adv7123";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7123_in: endpoint {
remote-endpoint = <&du_out_rgb1>;
};
};
port@1 {
reg = <1>;
adv7123_out: endpoint {
remote-endpoint = <&vga_in>;
};
};
};
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
};
vga {
compatible = "vga-connector";
port {
vga_in: endpoint {
remote-endpoint = <&adv7123_out>;
};
};
};
x1_clk: x1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <74250000>;
};
x2_clk: x2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <65000000>;
};
keyboard {
compatible = "gpio-keys";
key-1 {
linux,code = <KEY_1>;
label = "SW2-1";
wakeup-source;
debounce-interval = <20>;
gpios = <&gpio3 10 GPIO_ACTIVE_LOW>;
};
key-2 {
linux,code = <KEY_2>;
label = "SW2-2";
wakeup-source;
debounce-interval = <20>;
gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
};
key-3 {
linux,code = <KEY_3>;
label = "SW2-3";
wakeup-source;
debounce-interval = <20>;
gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
};
key-4 {
linux,code = <KEY_4>;
label = "SW2-4";
wakeup-source;
debounce-interval = <20>;
gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
};
key-a {
linux,code = <KEY_A>;
label = "SW24";
wakeup-source;
debounce-interval = <20>;
gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
};
key-b {
linux,code = <KEY_B>;
label = "SW25";
wakeup-source;
debounce-interval = <20>;
gpios = <&gpio11 2 GPIO_ACTIVE_LOW>;
};
};
leds {
compatible = "gpio-leds";
led17 {
gpios = <&gpio10 10 GPIO_ACTIVE_HIGH>;
};
led18 {
gpios = <&gpio10 11 GPIO_ACTIVE_HIGH>;
};
led19 {
gpios = <&gpio10 12 GPIO_ACTIVE_HIGH>;
};
led20 {
gpios = <&gpio10 23 GPIO_ACTIVE_HIGH>;
};
};
vcc_sdhi0: regulator-vcc-sdhi0 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio11 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&extal_clk {
@ -90,6 +222,21 @@
groups = "can0_data", "can_clk";
function = "can0";
};
sdhi0_pins: sdhi0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
};
du0_pins: du0 {
groups = "du0_rgb888", "du0_sync", "du0_disp";
function = "du0";
};
du1_pins: du1 {
groups = "du1_rgb666", "du1_sync", "du1_disp";
function = "du1";
};
};
&scif0 {
@ -112,3 +259,72 @@
status = "okay";
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-names = "default";
vmmc-supply = <&vcc_sdhi0>;
cd-gpios = <&gpio11 11 GPIO_ACTIVE_LOW>;
status = "okay";
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
hdmi@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupt-parent = <&irqc>;
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&du_out_rgb0>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con>;
};
};
};
};
};
&du {
pinctrl-0 = <&du0_pins &du1_pins>;
pinctrl-names = "default";
clocks = <&mstp7_clks R8A7792_CLK_DU0>, <&mstp7_clks R8A7792_CLK_DU1>,
<&x1_clk>, <&x2_clk>;
clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
status = "okay";
ports {
port@0 {
endpoint {
remote-endpoint = <&adv7511_in>;
};
};
port@1 {
endpoint {
remote-endpoint = <&adv7123_in>;
};
};
};
};

199
arch/arm/boot/dts/r8a7792-wheat.dts Normal file
View File

@ -0,0 +1,199 @@
/*
* Device Tree Source for the Wheat board
*
* Copyright (C) 2016 Renesas Electronics Corporation
* Copyright (C) 2016 Cogent Embedded, Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/dts-v1/;
#include "r8a7792.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Wheat";
compatible = "renesas,wheat", "renesas,r8a7792";
aliases {
serial0 = &scif0;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial0:115200n8";
};
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x40000000>;
};
d3_3v: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "D3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ethernet@18000000 {
compatible = "smsc,lan89218", "smsc,lan9115";
reg = <0 0x18000000 0 0x100>;
phy-mode = "mii";
interrupt-parent = <&irqc>;
interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
smsc,irq-push-pull;
smsc,save-mac-address;
reg-io-width = <4>;
vddvario-supply = <&d3_3v>;
vdd33a-supply = <&d3_3v>;
pinctrl-0 = <&lan89218_pins>;
pinctrl-names = "default";
};
keyboard {
compatible = "gpio-keys";
key-a {
linux,code = <KEY_A>;
label = "SW2";
wakeup-source;
debounce-interval = <20>;
gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
};
key-b {
linux,code = <KEY_B>;
label = "SW3";
wakeup-source;
debounce-interval = <20>;
gpios = <&gpio11 2 GPIO_ACTIVE_LOW>;
};
};
vcc_sdhi0: regulator-vcc-sdhi0 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio11 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&extal_clk {
clock-frequency = <20000000>;
};
&pfc {
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
};
lan89218_pins: lan89218 {
intc {
groups = "intc_irq0";
function = "intc";
};
lbsc {
groups = "lbsc_ex_cs0";
function = "lbsc";
};
};
can0_pins: can0 {
groups = "can0_data";
function = "can0";
};
can1_pins: can1 {
groups = "can1_data";
function = "can1";
};
sdhi0_pins: sdhi0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
};
qspi_pins: qspi {
groups = "qspi_ctrl", "qspi_data4";
function = "qspi";
};
};
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
status = "okay";
};
&can0 {
pinctrl-0 = <&can0_pins>;
pinctrl-names = "default";
status = "okay";
};
&can1 {
pinctrl-0 = <&can1_pins>;
pinctrl-names = "default";
status = "okay";
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-names = "default";
vmmc-supply = <&vcc_sdhi0>;
cd-gpios = <&gpio11 11 GPIO_ACTIVE_LOW>;
status = "okay";
};
&qspi {
pinctrl-0 = <&qspi_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spansion,s25fl512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <30000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-cpol;
spi-cpha;
m25p,fast-read;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "loader";
reg = <0x00000000 0x00040000>;
read-only;
};
partition@40000 {
label = "user";
reg = <0x00040000 0x00400000>;
read-only;
};
partition@440000 {
label = "flash";
reg = <0x00440000 0x03bc0000>;
};
};
};
};

58
arch/arm/boot/dts/r8a7792.dtsi
View File

@ -25,6 +25,7 @@
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
spi0 = &qspi;
vin0 = &vin0;
vin1 = &vin1;
vin2 = &vin2;
@ -556,6 +557,21 @@
status = "disabled";
};
qspi: spi@e6b10000 {
compatible = "renesas,qspi-r8a7792", "renesas,qspi";
reg = <0 0xe6b10000 0 0x2c>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7792_CLK_QSPI_MOD>;
dmas = <&dmac0 0x17>, <&dmac0 0x18>,
<&dmac1 0x17>, <&dmac1 0x18>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
du: display@feb00000 {
compatible = "renesas,du-r8a7792";
reg = <0 0xfeb00000 0 0x40000>;
@ -668,6 +684,30 @@
status = "disabled";
};
vsp1@fe928000 {
compatible = "renesas,vsp1";
reg = <0 0xfe928000 0 0x8000>;
interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7792_CLK_VSP1_SY>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
};
vsp1@fe930000 {
compatible = "renesas,vsp1";
reg = <0 0xfe930000 0 0x8000>;
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7792_CLK_VSP1DU0>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
};
vsp1@fe938000 {
compatible = "renesas,vsp1";
reg = <0 0xfe938000 0 0x8000>;
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7792_CLK_VSP1DU1>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
};
/* Special CPG clocks */
cpg_clocks: cpg_clocks@e6150000 {
compatible = "renesas,r8a7792-cpg-clocks",
@ -757,10 +797,15 @@
compatible = "renesas,r8a7792-mstp-clocks",
"renesas,cpg-mstp-clocks";
reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
clocks = <&m2_clk>;
clocks = <&m2_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
#clock-cells = <1>;
clock-indices = <R8A7792_CLK_JPU>;
clock-output-names = "jpu";
clock-indices = <
R8A7792_CLK_JPU
R8A7792_CLK_VSP1DU1 R8A7792_CLK_VSP1DU0
R8A7792_CLK_VSP1_SY
>;
clock-output-names = "jpu", "vsp1du1", "vsp1du0",
"vsp1-sy";
};
mstp2_clks: mstp2_clks@e6150138 {
compatible = "renesas,r8a7792-mstp-clocks",
@ -831,6 +876,7 @@
clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
<&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
<&cp_clk>, <&cp_clk>, <&p_clk>, <&p_clk>,
<&cpg_clocks R8A7792_CLK_QSPI>,
<&cp_clk>, <&cp_clk>, <&hp_clk>, <&hp_clk>,
<&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
#clock-cells = <1>;
@ -841,6 +887,7 @@
R8A7792_CLK_GPIO1 R8A7792_CLK_GPIO0
R8A7792_CLK_GPIO11 R8A7792_CLK_GPIO10
R8A7792_CLK_CAN1 R8A7792_CLK_CAN0
R8A7792_CLK_QSPI_MOD
R8A7792_CLK_GPIO9 R8A7792_CLK_GPIO8
R8A7792_CLK_I2C5 R8A7792_CLK_I2C4
R8A7792_CLK_I2C3 R8A7792_CLK_I2C2
@ -850,8 +897,9 @@
"gpio7", "gpio6", "gpio5", "gpio4",
"gpio3", "gpio2", "gpio1", "gpio0",
"gpio11", "gpio10", "can1", "can0",
"gpio9", "gpio8", "i2c5", "i2c4",
"i2c3", "i2c2", "i2c1", "i2c0";
"qspi_mod", "gpio9", "gpio8",
"i2c5", "i2c4", "i2c3", "i2c2",
"i2c1", "i2c0";
};
};

106
arch/arm/boot/dts/r8a7794-alt.dts
View File

@ -10,6 +10,7 @@
/dts-v1/;
#include "r8a7794.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Alt";
@ -29,6 +30,63 @@
reg = <0 0x40000000 0 0x40000000>;
};
d3_3v: regulator-d3-3v {
compatible = "regulator-fixed";
regulator-name = "D3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
vcc_sdhi0: regulator-vcc-sdhi0 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
vcc_sdhi1: regulator-vcc-sdhi1 {
compatible = "regulator-fixed";
regulator-name = "SDHI1 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi1: regulator-vccq-sdhi1 {
compatible = "regulator-gpio";
regulator-name = "SDHI1 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
lbsc {
#address-cells = <1>;
#size-cells = <1>;
@ -140,6 +198,21 @@
groups = "vin0_data8", "vin0_clk";
function = "vin0";
};
mmcif0_pins: mmcif0 {
groups = "mmc_data8", "mmc_ctrl";
function = "mmc";
};
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
};
sdhi1_pins: sd1 {
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
};
};
&cmt0 {
@ -169,6 +242,39 @@
};
};
&mmcif0 {
pinctrl-0 = <&mmcif0_pins>;
pinctrl-names = "default";
vmmc-supply = <&d3_3v>;
vqmmc-supply = <&d3_3v>;
bus-width = <8>;
non-removable;
status = "okay";
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-names = "default";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>;
status = "okay";
};
&sdhi1 {
pinctrl-0 = <&sdhi1_pins>;
pinctrl-names = "default";
vmmc-supply = <&vcc_sdhi1>;
vqmmc-supply = <&vccq_sdhi1>;
cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
status = "okay";
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";

18
arch/arm/boot/dts/r8a7794.dtsi
View File

@ -894,6 +894,22 @@
};
};
vsp1@fe928000 {
compatible = "renesas,vsp1";
reg = <0 0xfe928000 0 0x8000>;
interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7794_CLK_VSP1_S>;
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
};
vsp1@fe930000 {
compatible = "renesas,vsp1";
reg = <0 0xfe930000 0 0x8000>;
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7794_CLK_VSP1_DU0>;
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
};
du: display@feb00000 {
compatible = "renesas,du-r8a7794";
reg = <0 0xfeb00000 0 0x40000>;
@ -1235,7 +1251,7 @@
mstp5_clks: mstp5_clks@e6150144 {
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
clocks = <&hp_clk>, <&extal_clk>, <&p_clk>;
clocks = <&hp_clk>, <&p_clk>;
#clock-cells = <1>;
clock-indices = <R8A7794_CLK_AUDIO_DMAC0
R8A7794_CLK_PWM>;

3
include/dt-bindings/clock/r7s72100-clock.h
View File

@ -25,6 +25,9 @@
#define R7S72100_CLK_SCIF6 1
#define R7S72100_CLK_SCIF7 0
/* MSTP7 */
#define R7S72100_CLK_ETHER 4
/* MSTP9 */
#define R7S72100_CLK_I2C0 7
#define R7S72100_CLK_I2C1 6