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some more driver bugfixes and a DT binding conversion
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This commit is contained in:
Linus Torvalds
commit
a5e219005a
@ -1,35 +0,0 @@
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Broadcom Kona Family I2C
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=========================
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This I2C controller is used in the following Broadcom SoCs:
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BCM11130
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BCM11140
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BCM11351
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BCM28145
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BCM28155
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Required Properties
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-------------------
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- compatible: "brcm,bcm11351-i2c", "brcm,kona-i2c"
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- reg: Physical base address and length of controller registers
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- interrupts: The interrupt number used by the controller
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- clocks: clock specifier for the kona i2c external clock
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- clock-frequency: The I2C bus frequency in Hz
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- #address-cells: Should be <1>
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- #size-cells: Should be <0>
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Refer to clocks/clock-bindings.txt for generic clock consumer
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properties.
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Example:
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i2c@3e016000 {
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compatible = "brcm,bcm11351-i2c","brcm,kona-i2c";
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reg = <0x3e016000 0x80>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bsc1_clk>;
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clock-frequency = <400000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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59
Documentation/devicetree/bindings/i2c/brcm,kona-i2c.yaml
Normal file
59
Documentation/devicetree/bindings/i2c/brcm,kona-i2c.yaml
Normal file
@ -0,0 +1,59 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/i2c/brcm,kona-i2c.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Broadcom Kona family I2C controller
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maintainers:
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- Florian Fainelli <f.fainelli@gmail.com>
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allOf:
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- $ref: /schemas/i2c/i2c-controller.yaml#
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properties:
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compatible:
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items:
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- enum:
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- brcm,bcm11351-i2c
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- brcm,bcm21664-i2c
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- brcm,bcm23550-i2c
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- const: brcm,kona-i2c
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-frequency:
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enum: [ 100000, 400000, 1000000, 3400000 ]
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-frequency
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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i2c@3e016000 {
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compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c";
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reg = <0x3e016000 0x80>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bsc1_clk>;
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clock-frequency = <400000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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...
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@ -353,7 +353,6 @@ static void gxp_i2c_chk_data_ack(struct gxp_i2c_drvdata *drvdata)
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writew(value, drvdata->base + GXP_I2CMCMD);
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}
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#if IS_ENABLED(CONFIG_I2C_SLAVE)
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static bool gxp_i2c_slave_irq_handler(struct gxp_i2c_drvdata *drvdata)
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{
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u8 value;
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@ -437,7 +436,6 @@ static bool gxp_i2c_slave_irq_handler(struct gxp_i2c_drvdata *drvdata)
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return true;
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}
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#endif
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static irqreturn_t gxp_i2c_irq_handler(int irq, void *_drvdata)
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{
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@ -639,7 +639,7 @@ static int __maybe_unused lpi2c_runtime_suspend(struct device *dev)
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{
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struct lpi2c_imx_struct *lpi2c_imx = dev_get_drvdata(dev);
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clk_bulk_disable_unprepare(lpi2c_imx->num_clks, lpi2c_imx->clks);
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clk_bulk_disable(lpi2c_imx->num_clks, lpi2c_imx->clks);
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pinctrl_pm_select_sleep_state(dev);
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return 0;
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@ -651,7 +651,7 @@ static int __maybe_unused lpi2c_runtime_resume(struct device *dev)
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int ret;
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pinctrl_pm_select_default_state(dev);
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ret = clk_bulk_prepare_enable(lpi2c_imx->num_clks, lpi2c_imx->clks);
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ret = clk_bulk_enable(lpi2c_imx->num_clks, lpi2c_imx->clks);
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if (ret) {
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dev_err(dev, "failed to enable I2C clock, ret=%d\n", ret);
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return ret;
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@ -1058,7 +1058,7 @@ omap_i2c_isr(int irq, void *dev_id)
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u16 stat;
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stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG);
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mask = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG);
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mask = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG) & ~OMAP_I2C_STAT_NACK;
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if (stat & mask)
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ret = IRQ_WAKE_THREAD;
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@ -242,9 +242,10 @@ struct tegra_i2c_hw_feature {
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* @is_dvc: identifies the DVC I2C controller, has a different register layout
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* @is_vi: identifies the VI I2C controller, has a different register layout
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* @msg_complete: transfer completion notifier
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* @msg_buf_remaining: size of unsent data in the message buffer
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* @msg_len: length of message in current transfer
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* @msg_err: error code for completed message
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* @msg_buf: pointer to current message data
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* @msg_buf_remaining: size of unsent data in the message buffer
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* @msg_read: indicates that the transfer is a read access
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* @timings: i2c timings information like bus frequency
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* @multimaster_mode: indicates that I2C controller is in multi-master mode
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@ -277,6 +278,7 @@ struct tegra_i2c_dev {
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struct completion msg_complete;
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size_t msg_buf_remaining;
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unsigned int msg_len;
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int msg_err;
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u8 *msg_buf;
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@ -1169,7 +1171,7 @@ static void tegra_i2c_push_packet_header(struct tegra_i2c_dev *i2c_dev,
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else
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i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
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packet_header = msg->len - 1;
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packet_header = i2c_dev->msg_len - 1;
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if (i2c_dev->dma_mode && !i2c_dev->msg_read)
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*dma_buf++ = packet_header;
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@ -1242,20 +1244,32 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
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return err;
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i2c_dev->msg_buf = msg->buf;
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i2c_dev->msg_len = msg->len;
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/* The condition true implies smbus block read and len is already read */
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if (msg->flags & I2C_M_RECV_LEN && end_state != MSG_END_CONTINUE)
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i2c_dev->msg_buf = msg->buf + 1;
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i2c_dev->msg_buf_remaining = msg->len;
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i2c_dev->msg_err = I2C_ERR_NONE;
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i2c_dev->msg_read = !!(msg->flags & I2C_M_RD);
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reinit_completion(&i2c_dev->msg_complete);
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/*
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* For SMBUS block read command, read only 1 byte in the first transfer.
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* Adjust that 1 byte for the next transfer in the msg buffer and msg
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* length.
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*/
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if (msg->flags & I2C_M_RECV_LEN) {
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if (end_state == MSG_END_CONTINUE) {
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i2c_dev->msg_len = 1;
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} else {
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i2c_dev->msg_buf += 1;
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i2c_dev->msg_len -= 1;
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}
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}
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i2c_dev->msg_buf_remaining = i2c_dev->msg_len;
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if (i2c_dev->msg_read)
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xfer_size = msg->len;
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xfer_size = i2c_dev->msg_len;
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else
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xfer_size = msg->len + I2C_PACKET_HEADER_SIZE;
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xfer_size = i2c_dev->msg_len + I2C_PACKET_HEADER_SIZE;
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xfer_size = ALIGN(xfer_size, BYTES_PER_FIFO_WORD);
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@ -1295,7 +1309,7 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
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if (!i2c_dev->msg_read) {
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if (i2c_dev->dma_mode) {
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memcpy(i2c_dev->dma_buf + I2C_PACKET_HEADER_SIZE,
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msg->buf, msg->len);
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msg->buf, i2c_dev->msg_len);
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dma_sync_single_for_device(i2c_dev->dma_dev,
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i2c_dev->dma_phys,
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@ -1352,7 +1366,7 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
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i2c_dev->dma_phys,
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xfer_size, DMA_FROM_DEVICE);
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memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf, msg->len);
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memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf, i2c_dev->msg_len);
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}
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}
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@ -1408,8 +1422,8 @@ static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
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ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], MSG_END_CONTINUE);
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if (ret)
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break;
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/* Set the read byte as msg len */
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msgs[i].len = msgs[i].buf[0];
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/* Set the msg length from first byte */
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msgs[i].len += msgs[i].buf[0];
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dev_dbg(i2c_dev->dev, "reading %d bytes\n", msgs[i].len);
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}
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ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
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@ -385,7 +385,6 @@ static inline void i2c_set_clientdata(struct i2c_client *client, void *data)
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/* I2C slave support */
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#if IS_ENABLED(CONFIG_I2C_SLAVE)
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enum i2c_slave_event {
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I2C_SLAVE_READ_REQUESTED,
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I2C_SLAVE_WRITE_REQUESTED,
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@ -396,9 +395,10 @@ enum i2c_slave_event {
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int i2c_slave_register(struct i2c_client *client, i2c_slave_cb_t slave_cb);
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int i2c_slave_unregister(struct i2c_client *client);
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bool i2c_detect_slave_mode(struct device *dev);
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int i2c_slave_event(struct i2c_client *client,
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enum i2c_slave_event event, u8 *val);
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#if IS_ENABLED(CONFIG_I2C_SLAVE)
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bool i2c_detect_slave_mode(struct device *dev);
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#else
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static inline bool i2c_detect_slave_mode(struct device *dev) { return false; }
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#endif
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