Minki/linux
1
0
Fork 1
mirror of https://github.com/torvalds/linux.git synced 2024-12-04 10:01:41 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'remotes/lorenzo/pci/dwc'

Browse Source 
- Use generic config accessors for TI AM65x (K3) to fix regression (Kishon
  Vijay Abraham I)

- Move MSI Receiver init to dw_pcie_host_init() so it is re-initialized
  along with the RC in resume (Jisheng Zhang)

- Remove unused pcie_app_rd() (Jiapeng Chong)

- Move iATU detection earlier to fix regression (Hou Zhiqiang)

* remotes/lorenzo/pci/dwc:
  PCI: dwc: Move iATU detection earlier
  PCI: dwc/intel-gw: Remove unused function
  PCI: dwc: Move dw_pcie_msi_init() to dw_pcie_setup_rc()
  PCI: keystone: Let AM65 use the pci_ops defined in pcie-designware-host.c
This commit is contained in:
Bjorn Helgaas 2021-05-04 10:43:26 -05:00
commit a5166a194e
6 changed files with 16 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/pci/controller/dwc/pci-keystone.c
View File

@ -803,7 +803,8 @@ static int __init ks_pcie_host_init(struct pcie_port *pp)
int ret;
pp->bridge->ops = &ks_pcie_ops;
pp->bridge->child_ops = &ks_child_pcie_ops;
if (!ks_pcie->is_am6)
pp->bridge->child_ops = &ks_child_pcie_ops;
ret = ks_pcie_config_legacy_irq(ks_pcie);
if (ret)

2
drivers/pci/controller/dwc/pcie-designware-ep.c
View File

@ -705,6 +705,8 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
}
}
dw_pcie_iatu_detect(pci);
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
if (!res)
return -EINVAL;

4
drivers/pci/controller/dwc/pcie-designware-host.c
View File

@ -398,9 +398,9 @@ int dw_pcie_host_init(struct pcie_port *pp)
if (ret)
goto err_free_msi;
}
dw_pcie_iatu_detect(pci);
dw_pcie_setup_rc(pp);
dw_pcie_msi_init(pp);
if (!dw_pcie_link_up(pci) && pci->ops && pci->ops->start_link) {
ret = pci->ops->start_link(pci);
@ -551,6 +551,8 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
}
}
dw_pcie_msi_init(pp);
/* Setup RC BARs */
dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);
dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);

11
drivers/pci/controller/dwc/pcie-designware.c
View File

@ -660,11 +660,9 @@ static void dw_pcie_iatu_detect_regions(struct dw_pcie *pci)
pci->num_ob_windows = ob;
}
void dw_pcie_setup(struct dw_pcie *pci)
void dw_pcie_iatu_detect(struct dw_pcie *pci)
{
u32 val;
struct device *dev = pci->dev;
struct device_node *np = dev->of_node;
struct platform_device *pdev = to_platform_device(dev);
if (pci->version >= 0x480A || (!pci->version &&
@ -693,6 +691,13 @@ void dw_pcie_setup(struct dw_pcie *pci)
dev_info(pci->dev, "Detected iATU regions: %u outbound, %u inbound",
pci->num_ob_windows, pci->num_ib_windows);
}
void dw_pcie_setup(struct dw_pcie *pci)
{
u32 val;
struct device *dev = pci->dev;
struct device_node *np = dev->of_node;
if (pci->link_gen > 0)
dw_pcie_link_set_max_speed(pci, pci->link_gen);

1
drivers/pci/controller/dwc/pcie-designware.h
View File

@ -306,6 +306,7 @@ int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
enum dw_pcie_region_type type);
void dw_pcie_setup(struct dw_pcie *pci);
void dw_pcie_iatu_detect(struct dw_pcie *pci);
static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)
{

5
drivers/pci/controller/dwc/pcie-intel-gw.c
View File

@ -81,11 +81,6 @@ static void pcie_update_bits(void __iomem *base, u32 ofs, u32 mask, u32 val)
writel(val, base + ofs);
}
static inline u32 pcie_app_rd(struct intel_pcie_port *lpp, u32 ofs)
{
return readl(lpp->app_base + ofs);
}
static inline void pcie_app_wr(struct intel_pcie_port *lpp, u32 ofs, u32 val)
{
writel(val, lpp->app_base + ofs);