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This a large collection of clk driver updates and a handful of new SoC

Browse Source 
clk driver support. We have the usual Qualcomm clk drivers, along with
 clk drivers for the Sophgo and T-Head vendors, all to support some new
 SoCs.
 
 Nothing in particular stands out to me in the updates. There's the
 interconnect clk driver which exposes clks as interconnects, crossing
 subsystems. There's a bunch of janitorial things that are improving
 drivers in general like kmemdup_array() or fixing error paths. But
 overall the updates look normal to fix the description data which is
 usually the stuff that's wrong and/or untested.
 
 I really wanted to land a bunch of KUnit clk code that I've been working
 on whenever I get some free time but it turned into a pumpkin at the
 last minute so I dropped those patches. I'll let it soak in linux-next
 after the merge window closes. I have a suspicion that we're going to
 need to totally rework the clk framework to fix structural issues like
 locking, clk rate setting, and runtime PM usage. Having a bunch of unit
 tests for that will help make sure that all keeps working.
 
 Core:
  - Skip gate basic type KUnit tests on s390 due to lack of MMIO emulation
 
 New Drivers:
  - AP sub-system clock controller in the T-Head TH1520
  - Sophgo Sophon sg2042 clk driver
  - Qualcomm SM7150 camera, display and video clk drivers
  - Qualcomm QCM2290 GPU clk driver
  - Qualcomm QCS8386/QCS8084 NSS clk driver
  - Qualcomm SM8650 camera and video drivers
 
 Updates:
  - Add reset support to Airoha EN7581 clk driver
  - Add MODULE_DESCRIPTIONs to various clk drivers
  - Introduce helper logic to expose clock controllers as simple
    interconnect providers
  - Use the interconnect helper above on Qualcomm ipq9574
  - Add CLK_SET_RATE_PARENT to the remaining USB pipe clocks on Qualcomm
    X1Elite
  - Improve error handling in Qualcomm kpss-xcc driver
  - Mark Qualcomm SC8280XP LPASS clock controller regmap_config const
  - Export more clocks for Rockchip rk3128 peripherals
  - Convert Rockchip clk drivers to use kmemdup_array()
  - Drop CLK_NR_CLKS from Rockchip rk3128 and rk3188 binding headers
  - Make qcom_cc_really_probe() take a struct device to allow reuse in
    non-platform-drivers
  - Introduce prepare-only branch clock ops in the qcom clk driver to
    support clocks on buses that take locks
  - Describe parent/child relationship for Qualcomm SC7280 camera GDSCs
  - Support Qualcomm Huayra 2290 alpha PLL
  - Adjust the highest SDCC clock frequency on Qualcomm IPQ6018 to match
    HS200 support
  - Add missing PCIe PIPE clocks on Qualcomm IPQ9574
  - Fix various configurations and properties in the Qualcomm SA8775P,
    X1E80100 and SM7280 drivers
  - Park Qualcomm SM8350 GPU RCGs on XO while disabled
  - Remove unused CONFIG_QCOM_RPMCC Kconfig symbol
  - exynos-clkout: Remove usage of of_device_id table as .of_match_table,
    because the driver is instantiated as MFD cell, not as standalone platform
    driver.  Populated .of_match_table confused people few times to convert the
    code to device_get_match_data(), which broke the driver
  - Mark one Samsung UFS clock as critical, because having it off stops the
    system from shutdown
  - Use kmemdup_array() when applicable
  - Remove unused 'struct gates_data' from old sunxi driver library
  - Add GPADC clock and reset for Allwinner H616
  - Minor Amlogic S4 clock fixes
  - DT bindings Yaml conversion of the Amlogic AXG audio controller
  - Amlogic C3 clock controllers support
  - Amlogic clk flag added to skip init of already enabled PLLs and avoid relocking
  - Amlogic A1 DT bindings updates for system pll support
  - Add missing MODULE_DESCRIPTION where necessary
  - Remove obsolete clock DT binding header files
  - Add Battery Backup (VBATTB) and I2C clocks, resets, and power
    domains on Renesas RZ/G3S
  - Add audio clocks on Renesas R-Car V4M
  - Add video capture (ISPCS, CSI-2, VIN) clocks on Renesas R-Car V4M
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "This a large collection of clk driver updates and a handful of new SoC
  clk driver support.

  We have the usual Qualcomm clk drivers, along with clk drivers for the
  Sophgo and T-Head vendors, all to support some new SoCs.

  Nothing in particular stands out to me in the updates. There's the
  interconnect clk driver which exposes clks as interconnects, crossing
  subsystems. There's a bunch of janitorial things that are improving
  drivers in general like kmemdup_array() or fixing error paths. But
  overall the updates look normal to fix the description data which is
  usually the stuff that's wrong and/or untested.

  Core:
   - Skip gate basic type KUnit tests on s390 due to lack of MMIO
     emulation

  New Drivers:
   - AP sub-system clock controller in the T-Head TH1520
   - Sophgo Sophon sg2042 clk driver
   - Qualcomm SM7150 camera, display and video clk drivers
   - Qualcomm QCM2290 GPU clk driver
   - Qualcomm QCS8386/QCS8084 NSS clk driver
   - Qualcomm SM8650 camera and video drivers

  Updates:
   - Add reset support to Airoha EN7581 clk driver
   - Add MODULE_DESCRIPTIONs to various clk drivers
   - Introduce helper logic to expose clock controllers as simple
     interconnect providers
   - Use the interconnect helper above on Qualcomm ipq9574
   - Add CLK_SET_RATE_PARENT to the remaining USB pipe clocks on
     Qualcomm X1Elite
   - Improve error handling in Qualcomm kpss-xcc driver
   - Mark Qualcomm SC8280XP LPASS clock controller regmap_config const
   - Export more clocks for Rockchip rk3128 peripherals
   - Convert Rockchip clk drivers to use kmemdup_array()
   - Drop CLK_NR_CLKS from Rockchip rk3128 and rk3188 binding headers
   - Make qcom_cc_really_probe() take a struct device to allow reuse in
     non-platform-drivers
   - Introduce prepare-only branch clock ops in the qcom clk driver to
     support clocks on buses that take locks
   - Describe parent/child relationship for Qualcomm SC7280 camera GDSCs
   - Support Qualcomm Huayra 2290 alpha PLL
   - Adjust the highest SDCC clock frequency on Qualcomm IPQ6018 to
     match HS200 support
   - Add missing PCIe PIPE clocks on Qualcomm IPQ9574
   - Fix various configurations and properties in the Qualcomm SA8775P,
     X1E80100 and SM7280 drivers
   - Park Qualcomm SM8350 GPU RCGs on XO while disabled
   - Remove unused CONFIG_QCOM_RPMCC Kconfig symbol
   - exynos-clkout: Remove usage of of_device_id table as
     .of_match_table, because the driver is instantiated as MFD cell,
     not as standalone platform driver. Populated .of_match_table
     confused people few times to convert the code to
     device_get_match_data(), which broke the driver
   - Mark one Samsung UFS clock as critical, because having it off stops
     the system from shutdown
   - Use kmemdup_array() when applicable
   - Remove unused 'struct gates_data' from old sunxi driver library
   - Add GPADC clock and reset for Allwinner H616
   - Minor Amlogic S4 clock fixes
   - DT bindings Yaml conversion of the Amlogic AXG audio controller
   - Amlogic C3 clock controllers support
   - Amlogic clk flag added to skip init of already enabled PLLs and
     avoid relocking
   - Amlogic A1 DT bindings updates for system pll support
   - Add missing MODULE_DESCRIPTION where necessary
   - Remove obsolete clock DT binding header files
   - Add Battery Backup (VBATTB) and I2C clocks, resets, and power
     domains on Renesas RZ/G3S
   - Add audio clocks on Renesas R-Car V4M
   - Add video capture (ISPCS, CSI-2, VIN) clocks on Renesas R-Car V4M"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (135 commits)
  clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks
  dt-bindings: clock: Document T-Head TH1520 AP_SUBSYS controller
  clk: sophgo: Avoid -Wsometimes-uninitialized in sg2042_clk_pll_set_rate()
  clk/sophgo: Using BUG() instead of unreachable() in mmux_get_parent_id()
  clk: mxs: Use clamp() in clk_ref_round_rate() and clk_ref_set_rate()
  clk: sunxi-ng r40: Constify struct regmap_config
  clk: en7523: fix rate divider for slic and spi clocks
  clk: lpc32xx: Constify struct regmap_config
  clk: xilinx: Constify struct regmap_config
  clk: en7523: Remove PCIe reset open drain configuration for EN7581
  clk: en7523: Remove pcie prepare/unpreare callbacks for EN7581 SoC
  clk: en7523: Add reset-controller support for EN7581 SoC
  dt-bindings: clock: airoha: Add reset support to EN7581 clock binding
  dt-bindings: clock: mediatek: Document reset cells for MT8188 sys
  clk: mediatek: mt8173-infracfg: Handle unallocated infracfg when module
  dt-bindings: clock: mediatek: add syscon compatible for mt7622 pciesys
  dt-bindings: clock: sprd,sc9860-clk: convert to YAML
  dt-bindings: clock: qoriq-clock: convert to yaml format
  clk: qcom: Park shared RCGs upon registration
  clk: qcom: ipq9574: Use icc-clk for enabling NoC related clocks
  ...
This commit is contained in:
Linus Torvalds 2024-07-19 12:16:28 -07:00
commit a4f9285520
469 changed files with 16824 additions and 2234 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml
View File

@ -35,7 +35,7 @@ properties:
reg:
minItems: 2
maxItems: 3
maxItems: 4
"#clock-cells":
description:
@ -43,6 +43,10 @@ properties:
clocks.
const: 1
'#reset-cells':
description: ID of the controller reset line
const: 1
required:
- compatible
- reg
@ -60,6 +64,8 @@ allOf:
- description: scu base address
- description: misc scu base address
'#reset-cells': false
- if:
properties:
compatible:
@ -70,6 +76,7 @@ allOf:
items:
- description: scu base address
- description: misc scu base address
- description: reset base address
- description: pb scu base address
additionalProperties: false
@ -83,3 +90,19 @@ examples:
<0x1fb00000 0x1000>;
#clock-cells = <1>;
};
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
scuclk: clock-controller@1fa20000 {
compatible = "airoha,en7581-scu";
reg = <0x0 0x1fa20000 0x0 0x400>,
<0x0 0x1fb00000 0x0 0x90>,
<0x0 0x1fb00830 0x0 0x8>,
<0x0 0x1fbe3400 0x0 0xfc>;
#clock-cells = <1>;
#reset-cells = <1>;
};
};

9
Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml
View File

@ -30,6 +30,8 @@ properties:
- description: input fixed pll div7
- description: input hifi pll
- description: input oscillator (usually at 24MHz)
- description: input sys pll
minItems: 6 # sys_pll is optional
clock-names:
items:
@ -39,6 +41,8 @@ properties:
- const: fclk_div7
- const: hifi_pll
- const: xtal
- const: sys_pll
minItems: 6 # sys_pll is optional
required:
- compatible
@ -65,9 +69,10 @@ examples:
<&clkc_pll CLKID_FCLK_DIV5>,
<&clkc_pll CLKID_FCLK_DIV7>,
<&clkc_pll CLKID_HIFI_PLL>,
<&xtal>;
<&xtal>,
<&clkc_pll CLKID_SYS_PLL>;
clock-names = "fclk_div2", "fclk_div3",
"fclk_div5", "fclk_div7",
"hifi_pll", "xtal";
"hifi_pll", "xtal", "sys_pll";
};
};

9
Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
View File

@ -26,11 +26,15 @@ properties:
items:
- description: input fixpll_in
- description: input hifipll_in
- description: input syspll_in
minItems: 2 # syspll_in is optional
clock-names:
items:
- const: fixpll_in
- const: hifipll_in
- const: syspll_in
minItems: 2 # syspll_in is optional
required:
- compatible
@ -53,7 +57,8 @@ examples:
reg = <0 0x7c80 0 0x18c>;
#clock-cells = <1>;
clocks = <&clkc_periphs CLKID_FIXPLL_IN>,
<&clkc_periphs CLKID_HIFIPLL_IN>;
clock-names = "fixpll_in", "hifipll_in";
<&clkc_periphs CLKID_HIFIPLL_IN>,
<&clkc_periphs CLKID_SYSPLL_IN>;
clock-names = "fixpll_in", "hifipll_in", "syspll_in";
};
};

59
Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
View File

@ -1,59 +0,0 @@
* Amlogic AXG Audio Clock Controllers
The Amlogic AXG audio clock controller generates and supplies clock to the
other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
devices.
Required Properties:
- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D,
"amlogic,g12a-audio-clkc" for G12A,
"amlogic,sm1-audio-clkc" for S905X3.
- reg : physical base address of the clock controller and length of
memory mapped region.
- clocks : a list of phandle + clock-specifier pairs for the clocks listed
in clock-names.
- clock-names : must contain the following:
* "pclk" - Main peripheral bus clock
may contain the following:
* "mst_in[0-7]" - 8 input plls to generate clock signals
* "slv_sclk[0-9]" - 10 slave bit clocks provided by external
components.
* "slv_lrclk[0-9]" - 10 slave sample clocks provided by external
components.
- resets : phandle of the internal reset line
- #clock-cells : should be 1.
- #reset-cells : should be 1 on the g12a (and following) soc family
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be
used in device tree sources.
Example:
clkc_audio: clock-controller@0 {
compatible = "amlogic,axg-audio-clkc";
reg = <0x0 0x0 0x0 0xb4>;
#clock-cells = <1>;
clocks = <&clkc CLKID_AUDIO>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL3>,
<&clkc CLKID_HIFI_PLL>,
<&clkc CLKID_FCLK_DIV3>,
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_GP0_PLL>;
clock-names = "pclk",
"mst_in0",
"mst_in1",
"mst_in2",
"mst_in3",
"mst_in4",
"mst_in5",
"mst_in6",
"mst_in7";
resets = <&reset RESET_AUDIO>;
};

201
Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml Normal file
View File

@ -0,0 +1,201 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/amlogic,axg-audio-clkc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic AXG Audio Clock Controller
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
- Jerome Brunet <jbrunet@baylibre.com>
description:
The Amlogic AXG audio clock controller generates and supplies clock to the
other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
devices.
properties:
compatible:
enum:
- amlogic,axg-audio-clkc
- amlogic,g12a-audio-clkc
- amlogic,sm1-audio-clkc
'#clock-cells':
const: 1
'#reset-cells':
const: 1
reg:
maxItems: 1
clocks:
minItems: 1
items:
- description: main peripheral bus clock
- description: input plls to generate clock signals N0
- description: input plls to generate clock signals N1
- description: input plls to generate clock signals N2
- description: input plls to generate clock signals N3
- description: input plls to generate clock signals N4
- description: input plls to generate clock signals N5
- description: input plls to generate clock signals N6
- description: input plls to generate clock signals N7
- description: slave bit clock N0 provided by external components
- description: slave bit clock N1 provided by external components
- description: slave bit clock N2 provided by external components
- description: slave bit clock N3 provided by external components
- description: slave bit clock N4 provided by external components
- description: slave bit clock N5 provided by external components
- description: slave bit clock N6 provided by external components
- description: slave bit clock N7 provided by external components
- description: slave bit clock N8 provided by external components
- description: slave bit clock N9 provided by external components
- description: slave sample clock N0 provided by external components
- description: slave sample clock N1 provided by external components
- description: slave sample clock N2 provided by external components
- description: slave sample clock N3 provided by external components
- description: slave sample clock N4 provided by external components
- description: slave sample clock N5 provided by external components
- description: slave sample clock N6 provided by external components
- description: slave sample clock N7 provided by external components
- description: slave sample clock N8 provided by external components
- description: slave sample clock N9 provided by external components
clock-names:
minItems: 1
items:
- const: pclk
- const: mst_in0
- const: mst_in1
- const: mst_in2
- const: mst_in3
- const: mst_in4
- const: mst_in5
- const: mst_in6
- const: mst_in7
- const: slv_sclk0
- const: slv_sclk1
- const: slv_sclk2
- const: slv_sclk3
- const: slv_sclk4
- const: slv_sclk5
- const: slv_sclk6
- const: slv_sclk7
- const: slv_sclk8
- const: slv_sclk9
- const: slv_lrclk0
- const: slv_lrclk1
- const: slv_lrclk2
- const: slv_lrclk3
- const: slv_lrclk4
- const: slv_lrclk5
- const: slv_lrclk6
- const: slv_lrclk7
- const: slv_lrclk8
- const: slv_lrclk9
resets:
description: internal reset line
required:
- compatible
- '#clock-cells'
- reg
- clocks
- clock-names
- resets
allOf:
- if:
properties:
compatible:
contains:
enum:
- amlogic,g12a-audio-clkc
- amlogic,sm1-audio-clkc
then:
required:
- '#reset-cells'
else:
properties:
'#reset-cells': false
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/axg-clkc.h>
#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
apb {
#address-cells = <2>;
#size-cells = <2>;
clkc_audio: clock-controller@0 {
compatible = "amlogic,axg-audio-clkc";
reg = <0x0 0x0 0x0 0xb4>;
#clock-cells = <1>;
clocks = <&clkc CLKID_AUDIO>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL3>,
<&clkc CLKID_HIFI_PLL>,
<&clkc CLKID_FCLK_DIV3>,
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_GP0_PLL>,
<&slv_sclk0>,
<&slv_sclk1>,
<&slv_sclk2>,
<&slv_sclk3>,
<&slv_sclk4>,
<&slv_sclk5>,
<&slv_sclk6>,
<&slv_sclk7>,
<&slv_sclk8>,
<&slv_sclk9>,
<&slv_lrclk0>,
<&slv_lrclk1>,
<&slv_lrclk2>,
<&slv_lrclk3>,
<&slv_lrclk4>,
<&slv_lrclk5>,
<&slv_lrclk6>,
<&slv_lrclk7>,
<&slv_lrclk8>,
<&slv_lrclk9>;
clock-names = "pclk",
"mst_in0",
"mst_in1",
"mst_in2",
"mst_in3",
"mst_in4",
"mst_in5",
"mst_in6",
"mst_in7",
"slv_sclk0",
"slv_sclk1",
"slv_sclk2",
"slv_sclk3",
"slv_sclk4",
"slv_sclk5",
"slv_sclk6",
"slv_sclk7",
"slv_sclk8",
"slv_sclk9",
"slv_lrclk0",
"slv_lrclk1",
"slv_lrclk2",
"slv_lrclk3",
"slv_lrclk4",
"slv_lrclk5",
"slv_lrclk6",
"slv_lrclk7",
"slv_lrclk8",
"slv_lrclk9";
resets = <&reset RESET_AUDIO>;
};
};

120
Documentation/devicetree/bindings/clock/amlogic,c3-peripherals-clkc.yaml Normal file
View File

@ -0,0 +1,120 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/amlogic,c3-peripherals-clkc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic C3 series Peripheral Clock Controller
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
- Jerome Brunet <jbrunet@baylibre.com>
- Xianwei Zhao <xianwei.zhao@amlogic.com>
- Chuan Liu <chuan.liu@amlogic.com>
properties:
compatible:
const: amlogic,c3-peripherals-clkc
reg:
maxItems: 1
clocks:
minItems: 16
items:
- description: input oscillator (usually at 24MHz)
- description: input oscillators multiplexer
- description: input fix pll
- description: input fclk div 2
- description: input fclk div 2p5
- description: input fclk div 3
- description: input fclk div 4
- description: input fclk div 5
- description: input fclk div 7
- description: input gp0 pll
- description: input gp1 pll
- description: input hifi pll
- description: input sys clk
- description: input axi clk
- description: input sys pll div 16
- description: input cpu clk div 16
- description: input pad clock for rtc clk (optional)
clock-names:
minItems: 16
items:
- const: xtal_24m
- const: oscin
- const: fix
- const: fdiv2
- const: fdiv2p5
- const: fdiv3
- const: fdiv4
- const: fdiv5
- const: fdiv7
- const: gp0
- const: gp1
- const: hifi
- const: sysclk
- const: axiclk
- const: sysplldiv16
- const: cpudiv16
- const: pad_osc
"#clock-cells":
const: 1
required:
- compatible
- reg
- clocks
- clock-names
- "#clock-cells"
additionalProperties: false
examples:
- |
apb {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@0 {
compatible = "amlogic,c3-peripherals-clkc";
reg = <0x0 0x0 0x0 0x49c>;
#clock-cells = <1>;
clocks = <&xtal_24m>,
<&scmi_clk 8>,
<&scmi_clk 12>,
<&clkc_pll 3>,
<&clkc_pll 5>,
<&clkc_pll 7>,
<&clkc_pll 9>,
<&clkc_pll 11>,
<&clkc_pll 13>,
<&clkc_pll 15>,
<&scmi_clk 13>,
<&clkc_pll 17>,
<&scmi_clk 9>,
<&scmi_clk 10>,
<&scmi_clk 14>,
<&scmi_clk 15>;
clock-names = "xtal_24m",
"oscin",
"fix",
"fdiv2",
"fdiv2p5",
"fdiv3",
"fdiv4",
"fdiv5",
"fdiv7",
"gp0",
"gp1",
"hifi",
"sysclk",
"axiclk",
"sysplldiv16",
"cpudiv16";
};
};

59
Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml Normal file
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@ -0,0 +1,59 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/amlogic,c3-pll-clkc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic C3 series PLL Clock Controller
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
- Jerome Brunet <jbrunet@baylibre.com>
- Chuan Liu <chuan.liu@amlogic.com>
- Xianwei Zhao <xianwei.zhao@amlogic.com>
properties:
compatible:
const: amlogic,c3-pll-clkc
reg:
maxItems: 1
clocks:
items:
- description: input top pll
- description: input mclk pll
clock-names:
items:
- const: top
- const: mclk
"#clock-cells":
const: 1
required:
- compatible
- reg
- clocks
- clock-names
- "#clock-cells"
additionalProperties: false
examples:
- |
apb {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@8000 {
compatible = "amlogic,c3-pll-clkc";
reg = <0x0 0x8000 0x0 0x1a4>;
clocks = <&scmi_clk 2>,
<&scmi_clk 5>;
clock-names = "top", "mclk";
#clock-cells = <1>;
};
};

84
Documentation/devicetree/bindings/clock/fsl,qoriq-clock-legacy.yaml Normal file
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@ -0,0 +1,84 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/fsl,qoriq-clock-legacy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Legacy Clock Block on Freescale QorIQ Platforms
maintainers:
- Frank Li <Frank.Li@nxp.com>
description: |
These nodes are deprecated. Kernels should continue to support
device trees with these nodes, but new device trees should not use them.
Most of the bindings are from the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
properties:
compatible:
enum:
- fsl,qoriq-core-pll-1.0
- fsl,qoriq-core-pll-2.0
- fsl,qoriq-core-mux-1.0
- fsl,qoriq-core-mux-2.0
- fsl,qoriq-sysclk-1.0
- fsl,qoriq-sysclk-2.0
- fsl,qoriq-platform-pll-1.0
- fsl,qoriq-platform-pll-2.0
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 4
clock-names:
minItems: 1
maxItems: 4
clock-output-names:
minItems: 1
maxItems: 8
'#clock-cells':
minimum: 0
maximum: 1
required:
- compatible
- '#clock-cells'
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
enum:
- fsl,qoriq-sysclk-1.0
- fsl,qoriq-sysclk-2.0
then:
properties:
'#clock-cells':
const: 0
- if:
properties:
compatible:
contains:
enum:
- fsl,qoriq-core-pll-1.0
- fsl,qoriq-core-pll-2.0
then:
properties:
'#clock-cells':
const: 1
description: |
* 0 - equal to the PLL frequency
* 1 - equal to the PLL frequency divided by 2
* 2 - equal to the PLL frequency divided by 4

207
Documentation/devicetree/bindings/clock/fsl,qoriq-clock.yaml Normal file
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@ -0,0 +1,207 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/fsl,qoriq-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Clock Block on Freescale QorIQ Platforms
maintainers:
- Frank Li <Frank.Li@nxp.com>
description: |
Freescale QorIQ chips take primary clocking input from the external
SYSCLK signal. The SYSCLK input (frequency) is multiplied using
multiple phase locked loops (PLL) to create a variety of frequencies
which can then be passed to a variety of internal logic, including
cores and peripheral IP blocks.
Please refer to the Reference Manual for details.
All references to "1.0" and "2.0" refer to the QorIQ chassis version to
which the chip complies.
Chassis Version Example Chips
--------------- -------------
1.0 p4080, p5020, p5040
2.0 t4240
Clock Provider
The clockgen node should act as a clock provider, though in older device
trees the children of the clockgen node are the clock providers.
properties:
compatible:
oneOf:
- items:
- enum:
- fsl,p2041-clockgen
- fsl,p3041-clockgen
- fsl,p4080-clockgen
- fsl,p5020-clockgen
- fsl,p5040-clockgen
- const: fsl,qoriq-clockgen-1.0
- items:
- enum:
- fsl,t1023-clockgen
- fsl,t1024-clockgen
- fsl,t1040-clockgen
- fsl,t1042-clockgen
- fsl,t2080-clockgen
- fsl,t2081-clockgen
- fsl,t4240-clockgen
- const: fsl,qoriq-clockgen-2.0
- items:
- enum:
- fsl,b4420-clockgen
- fsl,b4860-clockgen
- const: fsl,b4-clockgen
- items:
- enum:
- fsl,ls1012a-clockgen
- fsl,ls1021a-clockgen
- fsl,ls1028a-clockgen
- fsl,ls1043a-clockgen
- fsl,ls1046a-clockgen
- fsl,ls1088a-clockgen
- fsl,ls2080a-clockgen
- fsl,lx2160a-clockgen
reg:
maxItems: 1
ranges: true
'#address-cells':
const: 1
'#size-cells':
const: 1
'#clock-cells':
const: 2
description: |
The first cell of the clock specifier is the clock type, and the
second cell is the clock index for the specified type.
Type# Name Index Cell
0 sysclk must be 0
1 cmux index (n in CLKCnCSR)
2 hwaccel index (n in CLKCGnHWACSR)
3 fman 0 for fm1, 1 for fm2
4 platform pll n=pll/(n+1). For example, when n=1,
that means output_freq=PLL_freq/2.
5 coreclk must be 0
clock-frequency:
description: Input system clock frequency (SYSCLK)
clocks:
items:
- description:
sysclk may be provided as an input clock. Either clock-frequency
or clocks must be provided.
- description:
A second input clock, called "coreclk", may be provided if
core PLLs are based on a different input clock from the
platform PLL.
minItems: 1
clock-names:
items:
- const: sysclk
- const: coreclk
patternProperties:
'^mux[0-9]@[a-f0-9]+$':
deprecated: true
$ref: fsl,qoriq-clock-legacy.yaml
'^sysclk(-[a-z0-9]+)?$':
deprecated: true
$ref: fsl,qoriq-clock-legacy.yaml
'^pll[0-9]@[a-f0-9]+$':
deprecated: true
$ref: fsl,qoriq-clock-legacy.yaml
'^platform\-pll@[a-f0-9]+$':
deprecated: true
$ref: fsl,qoriq-clock-legacy.yaml
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
/* clock provider example */
global-utilities@e1000 {
compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
reg = <0xe1000 0x1000>;
clock-frequency = <133333333>;
#clock-cells = <2>;
};
- |
/* Legacy example */
global-utilities@e1000 {
compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
reg = <0xe1000 0x1000>;
ranges = <0x0 0xe1000 0x1000>;
clock-frequency = <133333333>;
#address-cells = <1>;
#size-cells = <1>;
#clock-cells = <2>;
sysclk: sysclk {
compatible = "fsl,qoriq-sysclk-1.0";
clock-output-names = "sysclk";
#clock-cells = <0>;
};
pll0: pll0@800 {
compatible = "fsl,qoriq-core-pll-1.0";
reg = <0x800 0x4>;
#clock-cells = <1>;
clocks = <&sysclk>;
clock-output-names = "pll0", "pll0-div2";
};
pll1: pll1@820 {
compatible = "fsl,qoriq-core-pll-1.0";
reg = <0x820 0x4>;
#clock-cells = <1>;
clocks = <&sysclk>;
clock-output-names = "pll1", "pll1-div2";
};
mux0: mux0@0 {
compatible = "fsl,qoriq-core-mux-1.0";
reg = <0x0 0x4>;
#clock-cells = <0>;
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux0";
};
mux1: mux1@20 {
compatible = "fsl,qoriq-core-mux-1.0";
reg = <0x20 0x4>;
#clock-cells = <0>;
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux1";
};
platform-pll@c00 {
#clock-cells = <1>;
reg = <0xc00 0x4>;
compatible = "fsl,qoriq-platform-pll-1.0";
clocks = <&sysclk>;
clock-output-names = "platform-pll", "platform-pll-div2";
};
};

10
Documentation/devicetree/bindings/clock/mediatek,mt7622-pciesys.yaml
View File

@ -14,9 +14,11 @@ maintainers:
properties:
compatible:
enum:
- mediatek,mt7622-pciesys
- mediatek,mt7629-pciesys
oneOf:
- items:
- const: mediatek,mt7622-pciesys
- const: syscon
- const: mediatek,mt7629-pciesys
reg:
maxItems: 1
@ -38,7 +40,7 @@ additionalProperties: false
examples:
- |
clock-controller@1a100800 {
compatible = "mediatek,mt7622-pciesys";
compatible = "mediatek,mt7622-pciesys", "syscon";
reg = <0x1a100800 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;

3
Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml
View File

@ -39,6 +39,9 @@ properties:
'#clock-cells':
const: 1
'#reset-cells':
const: 1
required:
- compatible
- reg

29
Documentation/devicetree/bindings/clock/milbeaut-clock.yaml
View File

@ -40,38 +40,11 @@ required:
additionalProperties: false
examples:
# Clock controller node:
- |
m10v-clk-ctrl@1d021000 {
clock-controller@1d021000 {
compatible = "socionext,milbeaut-m10v-ccu";
reg = <0x1d021000 0x4000>;
#clock-cells = <1>;
clocks = <&clki40mhz>;
};
# Required an external clock for Clock controller node:
- |
clocks {
clki40mhz: clki40mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <40000000>;
};
/* other clocks */
};
# The clock consumer shall specify the desired clock-output of the clock
# controller as below by specifying output-id in its "clk" phandle cell.
# 2: uart
# 4: 32-bit timer
# 7: UHS-I/II
- |
serial@1e700010 {
compatible = "socionext,milbeaut-usio-uart";
reg = <0x1e700010 0x10>;
interrupts = <0 141 0x4>, <0 149 0x4>;
interrupt-names = "rx", "tx";
clocks = <&clk 2>;
};
...

20
Documentation/devicetree/bindings/clock/qcom,dispcc-sc8280xp.yaml
View File

@ -40,31 +40,19 @@ properties:
- description: DSI 1 PLL byte clock
- description: DSI 1 PLL DSI clock
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
power-domains:
items:
- description: MMCX power domain
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |

20
Documentation/devicetree/bindings/clock/qcom,dispcc-sm6350.yaml
View File

@ -37,28 +37,16 @@ properties:
- const: dp_phy_pll_link_clk
- const: dp_phy_pll_vco_div_clk
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |

46
Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
View File

@ -27,6 +27,7 @@ properties:
- qcom,sm8350-dispcc
clocks:
minItems: 7
items:
- description: Board XO source
- description: Byte clock from DSI PHY0
@ -35,8 +36,15 @@ properties:
- description: Pixel clock from DSI PHY1
- description: Link clock from DP PHY
- description: VCO DIV clock from DP PHY
- description: Link clock from eDP PHY
- description: VCO DIV clock from eDP PHY
- description: Link clock from DP1 PHY
- description: VCO DIV clock from DP1 PHY
- description: Link clock from DP2 PHY
- description: VCO DIV clock from DP2 PHY
clock-names:
minItems: 7
items:
- const: bi_tcxo
- const: dsi0_phy_pll_out_byteclk
@ -45,18 +53,12 @@ properties:
- const: dsi1_phy_pll_out_dsiclk
- const: dp_phy_pll_link_clk
- const: dp_phy_pll_vco_div_clk
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
- const: edp_phy_pll_link_clk
- const: edp_phy_pll_vco_div_clk
- const: dptx1_phy_pll_link_clk
- const: dptx1_phy_pll_vco_div_clk
- const: dptx2_phy_pll_link_clk
- const: dptx2_phy_pll_vco_div_clk
power-domains:
description:
@ -70,14 +72,26 @@ properties:
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
- if:
not:
properties:
compatible:
contains:
const: qcom,sc8180x-dispcc
then:
properties:
clocks:
maxItems: 7
clock-names:
maxItems: 7
unevaluatedProperties: false
examples:
- |

3
Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml
View File

@ -69,6 +69,8 @@ properties:
const: 1
deprecated: true
'#power-domain-cells': false
required:
- compatible
@ -81,7 +83,6 @@ examples:
reg = <0x00900000 0x4000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
thermal-sensor {
compatible = "qcom,msm8960-tsens";

1
Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml
View File

@ -51,6 +51,7 @@ properties:
required:
- compatible
- '#power-domain-cells'
unevaluatedProperties: false

3
Documentation/devicetree/bindings/clock/qcom,gcc-ipq4019.yaml
View File

@ -34,6 +34,8 @@ properties:
- const: xo
- const: sleep_clk
'#power-domain-cells': false
required:
- compatible
@ -45,7 +47,6 @@ examples:
compatible = "qcom,gcc-ipq4019";
reg = <0x1800000 0x60000>;
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
clocks = <&xo>, <&sleep_clk>;
clock-names = "xo", "sleep_clk";

3
Documentation/devicetree/bindings/clock/qcom,gcc-ipq6018.yaml
View File

@ -36,6 +36,8 @@ properties:
- const: xo
- const: sleep_clk
'#power-domain-cells': false
required:
- compatible
- clocks
@ -51,7 +53,6 @@ examples:
clocks = <&xo>, <&sleep_clk>;
clock-names = "xo", "sleep_clk";
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
};
...

3
Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
View File

@ -46,6 +46,8 @@ properties:
allOf:
- $ref: /schemas/thermal/qcom-tsens.yaml#
'#power-domain-cells': false
required:
- compatible
- clocks
@ -65,7 +67,6 @@ examples:
clock-names = "pxo", "cxo", "pll4";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
tsens: thermal-sensor {
compatible = "qcom,ipq8064-tsens";

1
Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml
View File

@ -39,6 +39,7 @@ properties:
required:
- compatible
- '#power-domain-cells'
unevaluatedProperties: false

4
Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml → Documentation/devicetree/bindings/clock/qcom,gcc-mdm9607.yaml
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-other.yaml#
$id: http://devicetree.org/schemas/clock/qcom,gcc-mdm9607.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller
@ -15,7 +15,6 @@ description: |
domains.
See also::
include/dt-bindings/clock/qcom,gcc-msm8953.h
include/dt-bindings/clock/qcom,gcc-mdm9607.h
allOf:
@ -28,6 +27,7 @@ properties:
required:
- compatible
- '#power-domain-cells'
unevaluatedProperties: false

50
Documentation/devicetree/bindings/clock/qcom,gcc-mdm9615.yaml Normal file
View File

@ -0,0 +1,50 @@
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-mdm9615.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains.
See also::
include/dt-bindings/clock/qcom,gcc-mdm9615.h
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
enum:
- qcom,gcc-mdm9615
clocks:
items:
- description: CXO clock
- description: PLL4 from LLC
'#power-domain-cells': false
required:
- compatible
unevaluatedProperties: false
examples:
- |
clock-controller@900000 {
compatible = "qcom,gcc-mdm9615";
reg = <0x900000 0x4000>;
#clock-cells = <1>;
#reset-cells = <1>;
clocks = <&cxo_board>,
<&lcc_pll4>;
};
...

3
Documentation/devicetree/bindings/clock/qcom,gcc-msm8660.yaml
View File

@ -34,6 +34,8 @@ properties:
- const: pxo
- const: cxo
'#power-domain-cells': false
required:
- compatible
@ -47,7 +49,6 @@ examples:
reg = <0x900000 0x4000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
clocks = <&pxo_board>, <&cxo_board>;
clock-names = "pxo", "cxo";
};

1
Documentation/devicetree/bindings/clock/qcom,gcc-msm8909.yaml
View File

@ -42,6 +42,7 @@ required:
- compatible
- clocks
- clock-names
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#

1
Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml
View File

@ -48,6 +48,7 @@ properties:
required:
- compatible
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#

1
Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml
View File

@ -42,6 +42,7 @@ required:
- compatible
- clocks
- clock-names
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#

1
Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml
View File

@ -41,6 +41,7 @@ properties:
required:
- compatible
- '#power-domain-cells'
unevaluatedProperties: false

1
Documentation/devicetree/bindings/clock/qcom,gcc-msm8976.yaml
View File

@ -49,6 +49,7 @@ required:
- clocks
- clock-names
- vdd_gfx-supply
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#

1
Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml
View File

@ -35,6 +35,7 @@ required:
- compatible
- clocks
- clock-names
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#

1
Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml
View File

@ -50,6 +50,7 @@ properties:
required:
- compatible
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#

1
Documentation/devicetree/bindings/clock/qcom,gcc-msm8998.yaml
View File

@ -38,6 +38,7 @@ required:
- compatible
- clocks
- clock-names
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#

1
Documentation/devicetree/bindings/clock/qcom,gcc-qcm2290.yaml
View File

@ -33,6 +33,7 @@ required:
- compatible
- clocks
- clock-names
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#

1
Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml
View File

@ -40,6 +40,7 @@ properties:
required:
- compatible
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#

1
Documentation/devicetree/bindings/clock/qcom,gcc-sc7180.yaml
View File

@ -40,6 +40,7 @@ required:
- compatible
- clocks
- clock-names
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#

1
Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
View File

@ -51,6 +51,7 @@ required:
- compatible
- clocks
- clock-names
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#

1
Documentation/devicetree/bindings/clock/qcom,gcc-sc8180x.yaml
View File

@ -40,6 +40,7 @@ required:
- clocks
- clock-names
- power-domains
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#

1
Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml
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@ -65,6 +65,7 @@ properties:
required:
- compatible
- clocks
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#

1
Documentation/devicetree/bindings/clock/qcom,gcc-sdm660.yaml
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@ -40,6 +40,7 @@ properties:
required:
- compatible
- '#power-domain-cells'
unevaluatedProperties: false

1
Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml
View File

@ -35,6 +35,7 @@ properties:
required:
- compatible
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#

1
Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml
View File

@ -34,6 +34,7 @@ required:
- compatible
- clocks
- clock-names
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#

1
Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml
View File

@ -39,6 +39,7 @@ required:
- compatible
- clocks
- clock-names
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#

1
Documentation/devicetree/bindings/clock/qcom,gcc-sm6115.yaml
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@ -33,6 +33,7 @@ required:
- compatible
- clocks
- clock-names
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#

1
Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml
View File

@ -33,6 +33,7 @@ required:
- compatible
- clocks
- clock-names
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#

1
Documentation/devicetree/bindings/clock/qcom,gcc-sm6350.yaml
View File

@ -35,6 +35,7 @@ required:
- compatible
- clocks
- clock-names
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#

1
Documentation/devicetree/bindings/clock/qcom,gcc-sm8150.yaml
View File

@ -34,6 +34,7 @@ required:
- compatible
- clocks
- clock-names
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#

1
Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
View File

@ -36,6 +36,7 @@ required:
- compatible
- clocks
- clock-names
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#

1
Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml
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@ -55,6 +55,7 @@ required:
- compatible
- clocks
- clock-names
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#

1
Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml
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@ -49,6 +49,7 @@ required:
- compatible
- clocks
- clock-names
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#

1
Documentation/devicetree/bindings/clock/qcom,gcc.yaml
View File

@ -35,7 +35,6 @@ required:
- reg
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: true

20
Documentation/devicetree/bindings/clock/qcom,gpucc-sdm660.yaml
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@ -33,28 +33,16 @@ properties:
- const: gcc_gpu_gpll0_clk
- const: gcc_gpu_gpll0_div_clk
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |

20
Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
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@ -56,25 +56,10 @@ properties:
vdd-gfx-supply:
description: Regulator supply for the VDD_GFX pads
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
# Require that power-domains and vdd-gfx-supply are not both present
@ -83,7 +68,10 @@ not:
- power-domains
- vdd-gfx-supply
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |

3
Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml
View File

@ -33,6 +33,8 @@ properties:
- description: UNIPHY RX clock source
- description: UNIPHY TX clk source
'#power-domain-cells': false
required:
- compatible
- clocks
@ -58,6 +60,5 @@ examples:
<&uniphy_tx_clk>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

3
Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
View File

@ -30,6 +30,8 @@ properties:
- description: PCIE 2lane x1 PHY pipe clock source (For second lane)
- description: USB PCIE wrapper pipe clock source
'#power-domain-cells': false
required:
- compatible
- clocks
@ -47,7 +49,6 @@ examples:
<&pcie_2lane_phy_pipe_clk_x1>,
<&usb_pcie_wrapper_pipe_clk>;
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
};
...

3
Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml
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@ -33,6 +33,8 @@ properties:
- description: PCIE30 PHY3 pipe clock source
- description: USB3 PHY pipe clock source
'#power-domain-cells': false
'#interconnect-cells':
const: 1
@ -60,6 +62,5 @@ examples:
<&usb3phy_0_cc_pipe_clk>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

20
Documentation/devicetree/bindings/clock/qcom,msm8998-gpucc.yaml
View File

@ -29,28 +29,16 @@ properties:
- const: xo
- const: gpll0
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |

86
Documentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml Normal file
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@ -0,0 +1,86 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,qca8k-nsscc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm NSS Clock & Reset Controller on QCA8386/QCA8084
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Luo Jie <quic_luoj@quicinc.com>
description: |
Qualcomm NSS clock control module provides the clocks and resets
on QCA8386(switch mode)/QCA8084(PHY mode)
See also::
include/dt-bindings/clock/qcom,qca8k-nsscc.h
include/dt-bindings/reset/qcom,qca8k-nsscc.h
properties:
compatible:
oneOf:
- const: qcom,qca8084-nsscc
- items:
- enum:
- qcom,qca8082-nsscc
- qcom,qca8085-nsscc
- qcom,qca8384-nsscc
- qcom,qca8385-nsscc
- qcom,qca8386-nsscc
- const: qcom,qca8084-nsscc
clocks:
items:
- description: Chip reference clock source
- description: UNIPHY0 RX 312P5M/125M clock source
- description: UNIPHY0 TX 312P5M/125M clock source
- description: UNIPHY1 RX 312P5M/125M clock source
- description: UNIPHY1 TX 312P5M/125M clock source
- description: UNIPHY1 RX 312P5M clock source
- description: UNIPHY1 TX 312P5M clock source
reg:
items:
- description: MDIO bus address for Clock & Reset Controller register
reset-gpios:
description: GPIO connected to the chip
maxItems: 1
required:
- compatible
- clocks
- reg
- reset-gpios
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
mdio {
#address-cells = <1>;
#size-cells = <0>;
clock-controller@18 {
compatible = "qcom,qca8084-nsscc";
reg = <0x18>;
reset-gpios = <&tlmm 51 GPIO_ACTIVE_LOW>;
clocks = <&pcs0_pll>,
<&qca8k_uniphy0_rx>,
<&qca8k_uniphy0_tx>,
<&qca8k_uniphy1_rx>,
<&qca8k_uniphy1_tx>,
<&qca8k_uniphy1_rx312p5m>,
<&qca8k_uniphy1_tx312p5m>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
};
...

20
Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml
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@ -37,28 +37,16 @@ properties:
- const: dsi0_phy_pll_out_byteclk
- const: dsi0_phy_pll_out_dsiclk
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |

1
Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml
View File

@ -31,6 +31,7 @@ properties:
required:
- compatible
- clocks
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#

1
Documentation/devicetree/bindings/clock/qcom,sa8775p-gcc.yaml
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@ -46,6 +46,7 @@ properties:
required:
- compatible
- clocks
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#

20
Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml
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@ -37,28 +37,16 @@ properties:
- const: dp_phy_pll_link_clk
- const: dp_phy_pll_vco_div_clk
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |

20
Documentation/devicetree/bindings/clock/qcom,sc7280-dispcc.yaml
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@ -41,28 +41,16 @@ properties:
- const: edp_phy_pll_link_clk
- const: edp_phy_pll_vco_div_clk
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |

20
Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml
View File

@ -46,28 +46,16 @@ properties:
- const: dp_link_clk_divsel_ten
- const: dp_vco_divided_clk_src_mux
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |

1
Documentation/devicetree/bindings/clock/qcom,sdx75-gcc.yaml
View File

@ -41,6 +41,7 @@ properties:
required:
- compatible
- clocks
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#

1
Documentation/devicetree/bindings/clock/qcom,sm4450-gcc.yaml
View File

@ -32,6 +32,7 @@ properties:
required:
- compatible
- clocks
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#

20
Documentation/devicetree/bindings/clock/qcom,sm6115-dispcc.yaml
View File

@ -28,27 +28,15 @@ properties:
- description: Pixel clock from DSI PHY0
- description: GPLL0 DISP DIV clock from GCC
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |

1
Documentation/devicetree/bindings/clock/qcom,sm6375-gcc.yaml
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@ -31,6 +31,7 @@ properties:
required:
- compatible
- clocks
- '#power-domain-cells'
unevaluatedProperties: false

60
Documentation/devicetree/bindings/clock/qcom,sm7150-camcc.yaml Normal file
View File

@ -0,0 +1,60 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm7150-camcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller on SM7150
maintainers:
- Danila Tikhonov <danila@jiaxyga.com>
- David Wronek <david@mainlining.org>
- Jens Reidel <adrian@travitia.xyz>
description: |
Qualcomm camera clock control module provides the clocks, resets and power
domains on SM7150.
See also:: include/dt-bindings/clock/qcom,sm7150-camcc.h
properties:
compatible:
const: qcom,sm7150-camcc
clocks:
items:
- description: Board XO source
- description: Board XO Active-Only source
- description: Sleep clock source
power-domains:
maxItems: 1
description:
CX power domain.
required:
- compatible
- clocks
- power-domains
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@ad00000 {
compatible = "qcom,sm7150-camcc";
reg = <0xad00000 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

75
Documentation/devicetree/bindings/clock/qcom,sm7150-dispcc.yaml Normal file
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@ -0,0 +1,75 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm7150-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller for SM7150
maintainers:
- Danila Tikhonov <danila@jiaxyga.com>
- David Wronek <david@mainlining.org>
- Jens Reidel <adrian@travitia.xyz>
description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on SM7150.
See also:: include/dt-bindings/clock/qcom,sm7150-dispcc.h
properties:
compatible:
const: qcom,sm7150-dispcc
clocks:
items:
- description: Board XO source
- description: Board Always On XO source
- description: GPLL0 source from GCC
- description: Sleep clock source
- description: Byte clock from MDSS DSI PHY0
- description: Pixel clock from MDSS DSI PHY0
- description: Byte clock from MDSS DSI PHY1
- description: Pixel clock from MDSS DSI PHY1
- description: Link clock from DP PHY
- description: VCO DIV clock from DP PHY
power-domains:
maxItems: 1
description:
CX power domain.
required:
- compatible
- clocks
- power-domains
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,sm7150-gcc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@af00000 {
compatible = "qcom,sm7150-dispcc";
reg = <0x0af00000 0x200000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
<&sleep_clk>,
<&mdss_dsi0_phy 0>,
<&mdss_dsi0_phy 1>,
<&mdss_dsi1_phy 0>,
<&mdss_dsi1_phy 1>,
<&dp_phy 0>,
<&dp_phy 1>;
power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

1
Documentation/devicetree/bindings/clock/qcom,sm7150-gcc.yaml
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@ -30,6 +30,7 @@ properties:
required:
- compatible
- clocks
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#

58
Documentation/devicetree/bindings/clock/qcom,sm7150-videocc.yaml Normal file
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@ -0,0 +1,58 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm7150-videocc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Video Clock & Reset Controller on SM7150
maintainers:
- Danila Tikhonov <danila@jiaxyga.com>
- David Wronek <david@mainlining.org>
- Jens Reidel <adrian@travitia.xyz>
description: |
Qualcomm video clock control module provides the clocks, resets and power
domains on SM7150.
See also:: include/dt-bindings/clock/qcom,videocc-sm7150.h
properties:
compatible:
const: qcom,sm7150-videocc
clocks:
items:
- description: Board XO source
- description: Board Always On XO source
power-domains:
maxItems: 1
description:
CX power domain.
required:
- compatible
- clocks
- power-domains
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
videocc: clock-controller@ab00000 {
compatible = "qcom,sm7150-videocc";
reg = <0x0ab00000 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>;
power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

20
Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml
View File

@ -40,18 +40,6 @@ properties:
- description: Link clock from DP PHY3
- description: VCO DIV clock from DP PHY3
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
power-domains:
description:
A phandle and PM domain specifier for the MMCX power domain.
@ -64,13 +52,13 @@ properties:
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |

20
Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
View File

@ -34,27 +34,15 @@ properties:
- description: GPLL0 main branch source
- description: GPLL0 div branch source
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |

20
Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
View File

@ -25,9 +25,6 @@ properties:
- qcom,sm8550-videocc
- qcom,sm8650-videocc
reg:
maxItems: 1
clocks:
items:
- description: Board XO source
@ -43,26 +40,17 @@ properties:
description:
A phandle to an OPP node describing required MMCX performance point.
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
required:
- compatible
- reg
- clocks
- power-domains
- required-opps
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |

20
Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml
View File

@ -45,18 +45,6 @@ properties:
- description: Link clock from DP PHY3
- description: VCO DIV clock from DP PHY3
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
power-domains:
description:
A phandle and PM domain specifier for the MMCX power domain.
@ -69,13 +57,13 @@ properties:
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |

1
Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml
View File

@ -34,6 +34,7 @@ properties:
required:
- compatible
- clocks
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#

1
Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml
View File

@ -35,6 +35,7 @@ properties:
required:
- compatible
- clocks
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#

36
Documentation/devicetree/bindings/clock/qcom,videocc.yaml
View File

@ -37,18 +37,6 @@ properties:
minItems: 1
maxItems: 3
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
power-domains:
description:
A phandle and PM domain specifier for the MMCX power domain.
@ -61,21 +49,19 @@ properties:
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
- if:
properties:
compatible:
enum:
- qcom,sc7180-videocc
- qcom,sdm845-videocc
- qcom,sm8150-videocc
then:
properties:
clocks:
@ -101,6 +87,22 @@ allOf:
- const: bi_tcxo
- const: bi_tcxo_ao
- if:
properties:
compatible:
enum:
- qcom,sm8150-videocc
then:
properties:
clocks:
items:
- description: AHB
- description: Board XO source
clock-names:
items:
- const: iface
- const: bi_tcxo
- if:
properties:
compatible:
@ -119,7 +121,7 @@ allOf:
- const: bi_tcxo
- const: bi_tcxo_ao
additionalProperties: false
unevaluatedProperties: false
examples:
- |

1
Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml
View File

@ -41,6 +41,7 @@ required:
- compatible
- clocks
- power-domains
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#

212
Documentation/devicetree/bindings/clock/qoriq-clock.txt
View File

@ -1,212 +0,0 @@
* Clock Block on Freescale QorIQ Platforms
Freescale QorIQ chips take primary clocking input from the external
SYSCLK signal. The SYSCLK input (frequency) is multiplied using
multiple phase locked loops (PLL) to create a variety of frequencies
which can then be passed to a variety of internal logic, including
cores and peripheral IP blocks.
Please refer to the Reference Manual for details.
All references to "1.0" and "2.0" refer to the QorIQ chassis version to
which the chip complies.
Chassis Version Example Chips
--------------- -------------
1.0 p4080, p5020, p5040
2.0 t4240, b4860
1. Clock Block Binding
Required properties:
- compatible: Should contain a chip-specific clock block compatible
string and (if applicable) may contain a chassis-version clock
compatible string.
Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
* "fsl,p2041-clockgen"
* "fsl,p3041-clockgen"
* "fsl,p4080-clockgen"
* "fsl,p5020-clockgen"
* "fsl,p5040-clockgen"
* "fsl,t1023-clockgen"
* "fsl,t1024-clockgen"
* "fsl,t1040-clockgen"
* "fsl,t1042-clockgen"
* "fsl,t2080-clockgen"
* "fsl,t2081-clockgen"
* "fsl,t4240-clockgen"
* "fsl,b4420-clockgen"
* "fsl,b4860-clockgen"
* "fsl,ls1012a-clockgen"
* "fsl,ls1021a-clockgen"
* "fsl,ls1028a-clockgen"
* "fsl,ls1043a-clockgen"
* "fsl,ls1046a-clockgen"
* "fsl,ls1088a-clockgen"
* "fsl,ls2080a-clockgen"
* "fsl,lx2160a-clockgen"
Chassis-version clock strings include:
* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
- reg: Describes the address of the device's resources within the
address space defined by its parent bus, and resource zero
represents the clock register set
Optional properties:
- ranges: Allows valid translation between child's address space and
parent's. Must be present if the device has sub-nodes.
- #address-cells: Specifies the number of cells used to represent
physical base addresses. Must be present if the device has
sub-nodes and set to 1 if present
- #size-cells: Specifies the number of cells used to represent
the size of an address. Must be present if the device has
sub-nodes and set to 1 if present
- clock-frequency: Input system clock frequency (SYSCLK)
- clocks: If clock-frequency is not specified, sysclk may be provided
as an input clock. Either clock-frequency or clocks must be
provided.
A second input clock, called "coreclk", may be provided if
core PLLs are based on a different input clock from the
platform PLL.
- clock-names: Required if a coreclk is present. Valid names are
"sysclk" and "coreclk".
2. Clock Provider
The clockgen node should act as a clock provider, though in older device
trees the children of the clockgen node are the clock providers.
When the clockgen node is a clock provider, #clock-cells = <2>.
The first cell of the clock specifier is the clock type, and the
second cell is the clock index for the specified type.
Type# Name Index Cell
0 sysclk must be 0
1 cmux index (n in CLKCnCSR)
2 hwaccel index (n in CLKCGnHWACSR)
3 fman 0 for fm1, 1 for fm2
4 platform pll n=pll/(n+1). For example, when n=1,
that means output_freq=PLL_freq/2.
5 coreclk must be 0
3. Example
clockgen: global-utilities@e1000 {
compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
clock-frequency = <133333333>;
reg = <0xe1000 0x1000>;
#clock-cells = <2>;
};
fman@400000 {
...
clocks = <&clockgen 3 0>;
...
};
}
4. Legacy Child Nodes
NOTE: These nodes are deprecated. Kernels should continue to support
device trees with these nodes, but new device trees should not use them.
Most of the bindings are from the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : Should include one of the following:
* "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
* "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
* "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
* "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
* "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
It takes parent's clock-frequency as its clock.
* "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
It takes parent's clock-frequency as its clock.
* "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
* "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
- #clock-cells: From common clock binding. The number of cells in a
clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
clock-specifier cell may take the following values:
* 0 - equal to the PLL frequency
* 1 - equal to the PLL frequency divided by 2
* 2 - equal to the PLL frequency divided by 4
Recommended properties:
- clocks: Should be the phandle of input parent clock
- clock-names: From common clock binding, indicates the clock name
- clock-output-names: From common clock binding, indicates the names of
output clocks
- reg: Should be the offset and length of clock block base address.
The length should be 4.
Legacy Example:
/ {
clockgen: global-utilities@e1000 {
compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
ranges = <0x0 0xe1000 0x1000>;
clock-frequency = <133333333>;
reg = <0xe1000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
sysclk: sysclk {
#clock-cells = <0>;
compatible = "fsl,qoriq-sysclk-1.0";
clock-output-names = "sysclk";
};
pll0: pll0@800 {
#clock-cells = <1>;
reg = <0x800 0x4>;
compatible = "fsl,qoriq-core-pll-1.0";
clocks = <&sysclk>;
clock-output-names = "pll0", "pll0-div2";
};
pll1: pll1@820 {
#clock-cells = <1>;
reg = <0x820 0x4>;
compatible = "fsl,qoriq-core-pll-1.0";
clocks = <&sysclk>;
clock-output-names = "pll1", "pll1-div2";
};
mux0: mux0@0 {
#clock-cells = <0>;
reg = <0x0 0x4>;
compatible = "fsl,qoriq-core-mux-1.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux0";
};
mux1: mux1@20 {
#clock-cells = <0>;
reg = <0x20 0x4>;
compatible = "fsl,qoriq-core-mux-1.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux1";
};
platform-pll: platform-pll@c00 {
#clock-cells = <1>;
reg = <0xc00 0x4>;
compatible = "fsl,qoriq-platform-pll-1.0";
clocks = <&sysclk>;
clock-output-names = "platform-pll", "platform-pll-div2";
};
};
};
Example for legacy clock consumer:
/ {
cpu0: PowerPC,e5500@0 {
...
clocks = <&mux0>;
...
};
};

2
Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
View File

@ -62,7 +62,7 @@ properties:
'#reset-cells':
description:
The single reset specifier cell must be the module number, as defined in
The single reset specifier cell must be the reset number, as defined in
<dt-bindings/clock/r9a0*-cpg.h>.
const: 1

61
Documentation/devicetree/bindings/clock/sophgo,sg2042-clkgen.yaml Normal file
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@ -0,0 +1,61 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/sophgo,sg2042-clkgen.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Sophgo SG2042 Clock Generator for divider/mux/gate
maintainers:
- Chen Wang <unicorn_wang@outlook.com>
properties:
compatible:
const: sophgo,sg2042-clkgen
reg:
maxItems: 1
clocks:
items:
- description: Main PLL
- description: Fixed PLL
- description: DDR PLL 0
- description: DDR PLL 1
clock-names:
items:
- const: mpll
- const: fpll
- const: dpll0
- const: dpll1
'#clock-cells':
const: 1
description:
See <dt-bindings/clock/sophgo,sg2042-clkgen.h> for valid indices.
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@30012000 {
compatible = "sophgo,sg2042-clkgen";
reg = <0x30012000 0x1000>;
clocks = <&pllclk 0>,
<&pllclk 1>,
<&pllclk 2>,
<&pllclk 3>;
clock-names = "mpll",
"fpll",
"dpll0",
"dpll1";
#clock-cells = <1>;
};

53
Documentation/devicetree/bindings/clock/sophgo,sg2042-pll.yaml Normal file
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@ -0,0 +1,53 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/sophgo,sg2042-pll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Sophgo SG2042 PLL Clock Generator
maintainers:
- Chen Wang <unicorn_wang@outlook.com>
properties:
compatible:
const: sophgo,sg2042-pll
reg:
maxItems: 1
clocks:
items:
- description: Oscillator(Clock Generation IC) for Main/Fixed PLL (25 MHz)
- description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz)
- description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz)
clock-names:
items:
- const: cgi_main
- const: cgi_dpll0
- const: cgi_dpll1
'#clock-cells':
const: 1
description:
See <dt-bindings/clock/sophgo,sg2042-pll.h> for valid indices.
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@10000000 {
compatible = "sophgo,sg2042-pll";
reg = <0x10000000 0x10000>;
clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>;
clock-names = "cgi_main", "cgi_dpll0", "cgi_dpll1";
#clock-cells = <1>;
};

49
Documentation/devicetree/bindings/clock/sophgo,sg2042-rpgate.yaml Normal file
View File

@ -0,0 +1,49 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/sophgo,sg2042-rpgate.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Sophgo SG2042 Gate Clock Generator for RP(riscv processors) subsystem
maintainers:
- Chen Wang <unicorn_wang@outlook.com>
properties:
compatible:
const: sophgo,sg2042-rpgate
reg:
maxItems: 1
clocks:
items:
- description: Gate clock for RP subsystem
clock-names:
items:
- const: rpgate
'#clock-cells':
const: 1
description:
See <dt-bindings/clock/sophgo,sg2042-rpgate.h> for valid indices.
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@20000000 {
compatible = "sophgo,sg2042-rpgate";
reg = <0x20000000 0x10000>;
clocks = <&clkgen 85>;
clock-names = "rpgate";
#clock-cells = <1>;
};

63
Documentation/devicetree/bindings/clock/sprd,sc9860-clk.txt
View File

@ -1,63 +0,0 @@
Spreadtrum SC9860 Clock Binding
------------------------
Required properties:
- compatible: should contain the following compatible strings:
- "sprd,sc9860-pmu-gate"
- "sprd,sc9860-pll"
- "sprd,sc9860-ap-clk"
- "sprd,sc9860-aon-prediv"
- "sprd,sc9860-apahb-gate"
- "sprd,sc9860-aon-gate"
- "sprd,sc9860-aonsecure-clk"
- "sprd,sc9860-agcp-gate"
- "sprd,sc9860-gpu-clk"
- "sprd,sc9860-vsp-clk"
- "sprd,sc9860-vsp-gate"
- "sprd,sc9860-cam-clk"
- "sprd,sc9860-cam-gate"
- "sprd,sc9860-disp-clk"
- "sprd,sc9860-disp-gate"
- "sprd,sc9860-apapb-gate"
- #clock-cells: must be 1
- clocks : Should be the input parent clock(s) phandle for the clock, this
property here just simply shows which clock group the clocks'
parents are in, since each clk node would represent many clocks
which are defined in the driver. The detailed dependency
relationship (i.e. how many parents and which are the parents)
are implemented in driver code.
Optional properties:
- reg: Contain the registers base address and length. It must be configured
only if no 'sprd,syscon' under the node.
- sprd,syscon: phandle to the syscon which is in the same address area with
the clock, and so we can get regmap for the clocks from the
syscon device.
Example:
pmu_gate: pmu-gate {
compatible = "sprd,sc9860-pmu-gate";
sprd,syscon = <&pmu_regs>;
clocks = <&ext_26m>;
#clock-cells = <1>;
};
pll: pll {
compatible = "sprd,sc9860-pll";
sprd,syscon = <&ana_regs>;
clocks = <&pmu_gate 0>;
#clock-cells = <1>;
};
ap_clk: clock-controller@20000000 {
compatible = "sprd,sc9860-ap-clk";
reg = <0 0x20000000 0 0x400>;
clocks = <&ext_26m>, <&pll 0>,
<&pmu_gate 0>;
#clock-cells = <1>;
};

159
Documentation/devicetree/bindings/clock/sprd,sc9860-clk.yaml Normal file
View File

@ -0,0 +1,159 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/sprd,sc9860-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Spreadtrum SC9860 clock
maintainers:
- Orson Zhai <orsonzhai@gmail.com>
- Baolin Wang <baolin.wang7@gmail.com>
- Chunyan Zhang <zhang.lyra@gmail.com>
properties:
compatible:
enum:
- sprd,sc9860-agcp-gate
- sprd,sc9860-aonsecure-clk
- sprd,sc9860-aon-gate
- sprd,sc9860-aon-prediv
- sprd,sc9860-apahb-gate
- sprd,sc9860-apapb-gate
- sprd,sc9860-ap-clk
- sprd,sc9860-cam-clk
- sprd,sc9860-cam-gate
- sprd,sc9860-disp-clk
- sprd,sc9860-disp-gate
- sprd,sc9860-gpu-clk
- sprd,sc9860-pll
- sprd,sc9860-pmu-gate
- sprd,sc9860-vsp-clk
- sprd,sc9860-vsp-gate
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 3
'#clock-cells':
const: 1
sprd,syscon:
$ref: /schemas/types.yaml#/definitions/phandle
description:
phandle to the syscon which is in the same address area with the
clock, and so we can get regmap for the clocks from the syscon device
required:
- compatible
- clocks
- '#clock-cells'
allOf:
- if:
properties:
compatible:
contains:
enum:
- sprd,sc9860-agcp-gate
- sprd,sc9860-aon-gate
- sprd,sc9860-apahb-gate
- sprd,sc9860-apapb-gate
- sprd,sc9860-cam-gate
- sprd,sc9860-disp-gate
- sprd,sc9860-gpu-clk
- sprd,sc9860-pll
- sprd,sc9860-pmu-gate
- sprd,sc9860-vsp-gate
then:
properties:
clocks:
maxItems: 1
- if:
properties:
compatible:
contains:
enum:
- sprd,sc9860-aonsecure-clk
- sprd,sc9860-cam-clk
- sprd,sc9860-disp-clk
- sprd,sc9860-vsp-clk
then:
properties:
clocks:
minItems: 2
maxItems: 2
- if:
properties:
compatible:
contains:
enum:
- sprd,sc9860-aon-prediv
- sprd,sc9860-ap-clk
then:
properties:
clocks:
minItems: 3
- if:
properties:
compatible:
contains:
enum:
- sprd,sc9860-aonsecure-clk
- sprd,sc9860-aon-prediv
- sprd,sc9860-ap-clk
- sprd,sc9860-cam-clk
- sprd,sc9860-disp-clk
- sprd,sc9860-gpu-clk
- sprd,sc9860-vsp-clk
then:
required:
- reg
properties:
sprd,syscon: false
- if:
properties:
compatible:
contains:
enum:
- sprd,sc9860-agcp-gate
- sprd,sc9860-aon-gate
- sprd,sc9860-apahb-gate
- sprd,sc9860-apapb-gate
- sprd,sc9860-cam-gate
- sprd,sc9860-disp-gate
- sprd,sc9860-pll
- sprd,sc9860-pmu-gate
- sprd,sc9860-vsp-gate
then:
required:
- sprd,syscon
properties:
reg: false
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
pmu-gate {
compatible = "sprd,sc9860-pmu-gate";
clocks = <&ext_26m>;
#clock-cells = <1>;
sprd,syscon = <&pmu_regs>;
};
clock-controller@20000000 {
compatible = "sprd,sc9860-ap-clk";
reg = <0 0x20000000 0 0x400>;
clocks = <&ext_26m>, <&pll 0>, <&pmu_gate 0>;
#clock-cells = <1>;
};
};
...

53
Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml Normal file
View File

@ -0,0 +1,53 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/thead,th1520-clk-ap.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: T-HEAD TH1520 AP sub-system clock controller
description: |
The T-HEAD TH1520 AP sub-system clock controller configures the
CPU, DPU, GMAC and TEE PLLs.
SoC reference manual
https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf
maintainers:
- Jisheng Zhang <jszhang@kernel.org>
- Wei Fu <wefu@redhat.com>
- Drew Fustini <dfustini@tenstorrent.com>
properties:
compatible:
const: thead,th1520-clk-ap
reg:
maxItems: 1
clocks:
items:
- description: main oscillator (24MHz)
"#clock-cells":
const: 1
description:
See <dt-bindings/clock/thead,th1520-clk-ap.h> for valid indices.
required:
- compatible
- reg
- clocks
- "#clock-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/thead,th1520-clk-ap.h>
clock-controller@ef010000 {
compatible = "thead,th1520-clk-ap";
reg = <0xef010000 0x1000>;
clocks = <&osc>;
#clock-cells = <1>;
};

3
MAINTAINERS
View File

@ -19569,7 +19569,10 @@ M: Fu Wei <wefu@redhat.com>
L: linux-riscv@lists.infradead.org
S: Maintained
T: git https://github.com/pdp7/linux.git
F: Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml
F: arch/riscv/boot/dts/thead/
F: drivers/clk/thead/clk-th1520-ap.c
F: include/dt-bindings/clock/thead,th1520-clk-ap.h
RNBD BLOCK DRIVERS
M: Md. Haris Iqbal <haris.iqbal@ionos.com>

2
drivers/clk/Kconfig
View File

@ -495,6 +495,7 @@ source "drivers/clk/starfive/Kconfig"
source "drivers/clk/sunxi/Kconfig"
source "drivers/clk/sunxi-ng/Kconfig"
source "drivers/clk/tegra/Kconfig"
source "drivers/clk/thead/Kconfig"
source "drivers/clk/stm32/Kconfig"
source "drivers/clk/ti/Kconfig"
source "drivers/clk/uniphier/Kconfig"
@ -514,6 +515,7 @@ config CLK_KUNIT_TEST
config CLK_GATE_KUNIT_TEST
tristate "Basic gate type Kunit test" if !KUNIT_ALL_TESTS
depends on KUNIT
depends on !S390
default KUNIT_ALL_TESTS
help
Kunit test for the basic clk gate type.

1
drivers/clk/Makefile
View File

@ -127,6 +127,7 @@ obj-y += starfive/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-y += sunxi-ng/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_ARCH_THEAD) += thead/
obj-y += ti/
obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
obj-$(CONFIG_ARCH_U8500) += ux500/

254
drivers/clk/clk-en7523.c
View File

@ -5,7 +5,11 @@
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/reset-controller.h>
#include <dt-bindings/clock/en7523-clk.h>
#include <dt-bindings/reset/airoha,en7581-reset.h>
#define RST_NR_PER_BANK 32
#define REG_PCI_CONTROL 0x88
#define REG_PCI_CONTROL_PERSTOUT BIT(29)
@ -33,13 +37,14 @@
#define REG_PCIE1_MEM_MASK 0x0c
#define REG_PCIE2_MEM 0x10
#define REG_PCIE2_MEM_MASK 0x14
#define REG_PCIE_RESET_OPEN_DRAIN 0x018c
#define REG_PCIE_RESET_OPEN_DRAIN_MASK GENMASK(2, 0)
#define REG_NP_SCU_PCIC 0x88
#define REG_NP_SCU_SSTR 0x9c
#define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13)
#define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11)
#define REG_RST_CTRL2 0x00
#define REG_RST_CTRL1 0x04
struct en_clk_desc {
int id;
const char *name;
@ -57,6 +62,7 @@ struct en_clk_desc {
u8 div_shift;
u16 div_val0;
u8 div_step;
u8 div_offset;
};
struct en_clk_gate {
@ -64,10 +70,21 @@ struct en_clk_gate {
struct clk_hw hw;
};
struct en_rst_data {
const u16 *bank_ofs;
const u16 *idx_map;
void __iomem *base;
struct reset_controller_dev rcdev;
};
struct en_clk_soc_data {
const struct clk_ops pcie_ops;
int (*hw_init)(struct platform_device *pdev, void __iomem *base,
void __iomem *np_base);
struct {
const u16 *bank_ofs;
const u16 *idx_map;
u16 idx_map_nr;
} reset;
int (*hw_init)(struct platform_device *pdev, void __iomem *np_base);
};
static const u32 gsw_base[] = { 400000000, 500000000 };
@ -90,6 +107,7 @@ static const struct en_clk_desc en7523_base_clks[] = {
.div_bits = 3,
.div_shift = 0,
.div_step = 1,
.div_offset = 1,
}, {
.id = EN7523_CLK_EMI,
.name = "emi",
@ -103,6 +121,7 @@ static const struct en_clk_desc en7523_base_clks[] = {
.div_bits = 3,
.div_shift = 0,
.div_step = 1,
.div_offset = 1,
}, {
.id = EN7523_CLK_BUS,
.name = "bus",
@ -116,6 +135,7 @@ static const struct en_clk_desc en7523_base_clks[] = {
.div_bits = 3,
.div_shift = 0,
.div_step = 1,
.div_offset = 1,
}, {
.id = EN7523_CLK_SLIC,
.name = "slic",
@ -156,18 +176,82 @@ static const struct en_clk_desc en7523_base_clks[] = {
.div_bits = 3,
.div_shift = 0,
.div_step = 1,
.div_offset = 1,
}, {
.id = EN7523_CLK_CRYPTO,
.name = "crypto",
.base_reg = REG_CRYPTO_CLKSRC,
.base_bits = 1,
.base_shift = 8,
.base_shift = 0,
.base_values = emi_base,
.n_base_values = ARRAY_SIZE(emi_base),
}
};
static const u16 en7581_rst_ofs[] = {
REG_RST_CTRL2,
REG_RST_CTRL1,
};
static const u16 en7581_rst_map[] = {
/* RST_CTRL2 */
[EN7581_XPON_PHY_RST] = 0,
[EN7581_CPU_TIMER2_RST] = 2,
[EN7581_HSUART_RST] = 3,
[EN7581_UART4_RST] = 4,
[EN7581_UART5_RST] = 5,
[EN7581_I2C2_RST] = 6,
[EN7581_XSI_MAC_RST] = 7,
[EN7581_XSI_PHY_RST] = 8,
[EN7581_NPU_RST] = 9,
[EN7581_I2S_RST] = 10,
[EN7581_TRNG_RST] = 11,
[EN7581_TRNG_MSTART_RST] = 12,
[EN7581_DUAL_HSI0_RST] = 13,
[EN7581_DUAL_HSI1_RST] = 14,
[EN7581_HSI_RST] = 15,
[EN7581_DUAL_HSI0_MAC_RST] = 16,
[EN7581_DUAL_HSI1_MAC_RST] = 17,
[EN7581_HSI_MAC_RST] = 18,
[EN7581_WDMA_RST] = 19,
[EN7581_WOE0_RST] = 20,
[EN7581_WOE1_RST] = 21,
[EN7581_HSDMA_RST] = 22,
[EN7581_TDMA_RST] = 24,
[EN7581_EMMC_RST] = 25,
[EN7581_SOE_RST] = 26,
[EN7581_PCIE2_RST] = 27,
[EN7581_XFP_MAC_RST] = 28,
[EN7581_USB_HOST_P1_RST] = 29,
[EN7581_USB_HOST_P1_U3_PHY_RST] = 30,
/* RST_CTRL1 */
[EN7581_PCM1_ZSI_ISI_RST] = RST_NR_PER_BANK + 0,
[EN7581_FE_PDMA_RST] = RST_NR_PER_BANK + 1,
[EN7581_FE_QDMA_RST] = RST_NR_PER_BANK + 2,
[EN7581_PCM_SPIWP_RST] = RST_NR_PER_BANK + 4,
[EN7581_CRYPTO_RST] = RST_NR_PER_BANK + 6,
[EN7581_TIMER_RST] = RST_NR_PER_BANK + 8,
[EN7581_PCM1_RST] = RST_NR_PER_BANK + 11,
[EN7581_UART_RST] = RST_NR_PER_BANK + 12,
[EN7581_GPIO_RST] = RST_NR_PER_BANK + 13,
[EN7581_GDMA_RST] = RST_NR_PER_BANK + 14,
[EN7581_I2C_MASTER_RST] = RST_NR_PER_BANK + 16,
[EN7581_PCM2_ZSI_ISI_RST] = RST_NR_PER_BANK + 17,
[EN7581_SFC_RST] = RST_NR_PER_BANK + 18,
[EN7581_UART2_RST] = RST_NR_PER_BANK + 19,
[EN7581_GDMP_RST] = RST_NR_PER_BANK + 20,
[EN7581_FE_RST] = RST_NR_PER_BANK + 21,
[EN7581_USB_HOST_P0_RST] = RST_NR_PER_BANK + 22,
[EN7581_GSW_RST] = RST_NR_PER_BANK + 23,
[EN7581_SFC2_PCM_RST] = RST_NR_PER_BANK + 25,
[EN7581_PCIE0_RST] = RST_NR_PER_BANK + 26,
[EN7581_PCIE1_RST] = RST_NR_PER_BANK + 27,
[EN7581_CPU_TIMER_RST] = RST_NR_PER_BANK + 28,
[EN7581_PCIE_HB_RST] = RST_NR_PER_BANK + 29,
[EN7581_XPON_MAC_RST] = RST_NR_PER_BANK + 31,
};
static unsigned int en7523_get_base_rate(void __iomem *base, unsigned int i)
{
const struct en_clk_desc *desc = &en7523_base_clks[i];
@ -202,7 +286,7 @@ static u32 en7523_get_div(void __iomem *base, int i)
if (!val && desc->div_val0)
return desc->div_val0;
return (val + 1) * desc->div_step;
return (val + desc->div_offset) * desc->div_step;
}
static int en7523_pci_is_enabled(struct clk_hw *hw)
@ -279,9 +363,8 @@ static struct clk_hw *en7523_register_pcie_clk(struct device *dev,
cg->base = np_base;
cg->hw.init = &init;
if (init.ops->disable)
init.ops->disable(&cg->hw);
init.ops->unprepare(&cg->hw);
if (init.ops->unprepare)
init.ops->unprepare(&cg->hw);
if (clk_hw_register(dev, &cg->hw))
return NULL;
@ -299,23 +382,6 @@ static int en7581_pci_is_enabled(struct clk_hw *hw)
return (val & mask) == mask;
}
static int en7581_pci_prepare(struct clk_hw *hw)
{
struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
void __iomem *np_base = cg->base;
u32 val, mask;
mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 |
REG_RESET_CONTROL_PCIEHB;
val = readl(np_base + REG_RESET_CONTROL1);
writel(val & ~mask, np_base + REG_RESET_CONTROL1);
val = readl(np_base + REG_RESET_CONTROL2);
writel(val & ~REG_RESET2_CONTROL_PCIE2, np_base + REG_RESET_CONTROL2);
usleep_range(5000, 10000);
return 0;
}
static int en7581_pci_enable(struct clk_hw *hw)
{
struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
@ -332,23 +398,6 @@ static int en7581_pci_enable(struct clk_hw *hw)
return 0;
}
static void en7581_pci_unprepare(struct clk_hw *hw)
{
struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
void __iomem *np_base = cg->base;
u32 val, mask;
mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 |
REG_RESET_CONTROL_PCIEHB;
val = readl(np_base + REG_RESET_CONTROL1);
writel(val | mask, np_base + REG_RESET_CONTROL1);
mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2;
writel(val | mask, np_base + REG_RESET_CONTROL1);
val = readl(np_base + REG_RESET_CONTROL2);
writel(val | REG_RESET_CONTROL_PCIE2, np_base + REG_RESET_CONTROL2);
msleep(100);
}
static void en7581_pci_disable(struct clk_hw *hw)
{
struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
@ -364,13 +413,12 @@ static void en7581_pci_disable(struct clk_hw *hw)
}
static int en7581_clk_hw_init(struct platform_device *pdev,
void __iomem *base,
void __iomem *np_base)
{
void __iomem *pb_base;
u32 val;
pb_base = devm_platform_ioremap_resource(pdev, 2);
pb_base = devm_platform_ioremap_resource(pdev, 3);
if (IS_ERR(pb_base))
return PTR_ERR(pb_base);
@ -387,10 +435,6 @@ static int en7581_clk_hw_init(struct platform_device *pdev,
writel(0x28000000, pb_base + REG_PCIE2_MEM);
writel(0xfc000000, pb_base + REG_PCIE2_MEM_MASK);
val = readl(base + REG_PCIE_RESET_OPEN_DRAIN);
writel(val | REG_PCIE_RESET_OPEN_DRAIN_MASK,
base + REG_PCIE_RESET_OPEN_DRAIN);
return 0;
}
@ -423,6 +467,95 @@ static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_dat
clk_data->num = EN7523_NUM_CLOCKS;
}
static int en7523_reset_update(struct reset_controller_dev *rcdev,
unsigned long id, bool assert)
{
struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev);
void __iomem *addr = rst_data->base + rst_data->bank_ofs[id / RST_NR_PER_BANK];
u32 val;
val = readl(addr);
if (assert)
val |= BIT(id % RST_NR_PER_BANK);
else
val &= ~BIT(id % RST_NR_PER_BANK);
writel(val, addr);
return 0;
}
static int en7523_reset_assert(struct reset_controller_dev *rcdev,
unsigned long id)
{
return en7523_reset_update(rcdev, id, true);
}
static int en7523_reset_deassert(struct reset_controller_dev *rcdev,
unsigned long id)
{
return en7523_reset_update(rcdev, id, false);
}
static int en7523_reset_status(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev);
void __iomem *addr = rst_data->base + rst_data->bank_ofs[id / RST_NR_PER_BANK];
return !!(readl(addr) & BIT(id % RST_NR_PER_BANK));
}
static int en7523_reset_xlate(struct reset_controller_dev *rcdev,
const struct of_phandle_args *reset_spec)
{
struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev);
if (reset_spec->args[0] >= rcdev->nr_resets)
return -EINVAL;
return rst_data->idx_map[reset_spec->args[0]];
}
static const struct reset_control_ops en7523_reset_ops = {
.assert = en7523_reset_assert,
.deassert = en7523_reset_deassert,
.status = en7523_reset_status,
};
static int en7523_reset_register(struct platform_device *pdev,
const struct en_clk_soc_data *soc_data)
{
struct device *dev = &pdev->dev;
struct en_rst_data *rst_data;
void __iomem *base;
/* no reset lines available */
if (!soc_data->reset.idx_map_nr)
return 0;
base = devm_platform_ioremap_resource(pdev, 2);
if (IS_ERR(base))
return PTR_ERR(base);
rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL);
if (!rst_data)
return -ENOMEM;
rst_data->bank_ofs = soc_data->reset.bank_ofs;
rst_data->idx_map = soc_data->reset.idx_map;
rst_data->base = base;
rst_data->rcdev.nr_resets = soc_data->reset.idx_map_nr;
rst_data->rcdev.of_xlate = en7523_reset_xlate;
rst_data->rcdev.ops = &en7523_reset_ops;
rst_data->rcdev.of_node = dev->of_node;
rst_data->rcdev.of_reset_n_cells = 1;
rst_data->rcdev.owner = THIS_MODULE;
rst_data->rcdev.dev = dev;
return devm_reset_controller_register(dev, &rst_data->rcdev);
}
static int en7523_clk_probe(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
@ -441,7 +574,7 @@ static int en7523_clk_probe(struct platform_device *pdev)
soc_data = device_get_match_data(&pdev->dev);
if (soc_data->hw_init) {
r = soc_data->hw_init(pdev, base, np_base);
r = soc_data->hw_init(pdev, np_base);
if (r)
return r;
}
@ -456,11 +589,17 @@ static int en7523_clk_probe(struct platform_device *pdev)
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
pdev->name, r);
return dev_err_probe(&pdev->dev, r, "Could not register clock provider: %s\n",
pdev->name);
return r;
r = en7523_reset_register(pdev, soc_data);
if (r) {
of_clk_del_provider(node);
return dev_err_probe(&pdev->dev, r, "Could not register reset controller: %s\n",
pdev->name);
}
return 0;
}
static const struct en_clk_soc_data en7523_data = {
@ -474,11 +613,14 @@ static const struct en_clk_soc_data en7523_data = {
static const struct en_clk_soc_data en7581_data = {
.pcie_ops = {
.is_enabled = en7581_pci_is_enabled,
.prepare = en7581_pci_prepare,
.enable = en7581_pci_enable,
.unprepare = en7581_pci_unprepare,
.disable = en7581_pci_disable,
},
.reset = {
.bank_ofs = en7581_rst_ofs,
.idx_map = en7581_rst_map,
.idx_map_nr = ARRAY_SIZE(en7581_rst_map),
},
.hw_init = en7581_clk_hw_init,
};

3
drivers/clk/clk-fractional-divider_test.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Kunit test for clock fractional divider
* Kunit tests for clk fractional divider
*/
#include <linux/clk-provider.h>
#include <kunit/test.h>
@ -144,4 +144,5 @@ static struct kunit_suite clk_fd_approximation_suite = {
kunit_test_suites(
&clk_fd_approximation_suite
);
MODULE_DESCRIPTION("Kunit tests for clk fractional divider");
MODULE_LICENSE("GPL");

3
drivers/clk/clk-gate_test.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Kunit test for clk gate basic type
* Kunit tests for clk gate
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
@ -461,4 +461,5 @@ kunit_test_suites(
&clk_gate_test_hiword_suite,
&clk_gate_test_enabled_suite
);
MODULE_DESCRIPTION("Kunit tests for clk gate");
MODULE_LICENSE("GPL v2");

3
drivers/clk/clk_test.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Kunit test for clk rate management
* Kunit tests for clk framework
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
@ -2674,4 +2674,5 @@ kunit_test_suites(
&clk_single_parent_mux_test_suite,
&clk_uncached_test_suite
);
MODULE_DESCRIPTION("Kunit tests for clk framework");
MODULE_LICENSE("GPL v2");

2
drivers/clk/mediatek/clk-mt2701-aud.c
View File

@ -165,4 +165,6 @@ static struct platform_driver clk_mt2701_aud_drv = {
},
};
module_platform_driver(clk_mt2701_aud_drv);
MODULE_DESCRIPTION("MediaTek MT2701 audio clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt2701-bdp.c
View File

@ -106,4 +106,6 @@ static struct platform_driver clk_mt2701_bdp_drv = {
},
};
module_platform_driver(clk_mt2701_bdp_drv);
MODULE_DESCRIPTION("MediaTek MT2701 BDP clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt2701-eth.c
View File

@ -60,4 +60,6 @@ static struct platform_driver clk_mt2701_eth_drv = {
},
};
module_platform_driver(clk_mt2701_eth_drv);
MODULE_DESCRIPTION("MediaTek MT2701 Ethernet clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt2701-g3d.c
View File

@ -57,4 +57,6 @@ static struct platform_driver clk_mt2701_g3d_drv = {
},
};
module_platform_driver(clk_mt2701_g3d_drv);
MODULE_DESCRIPTION("MediaTek MT2701 GPU g3d clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt2701-hif.c
View File

@ -57,4 +57,6 @@ static struct platform_driver clk_mt2701_hif_drv = {
},
};
module_platform_driver(clk_mt2701_hif_drv);
MODULE_DESCRIPTION("MediaTek MT2701 HIFSYS clocks driver");
MODULE_LICENSE("GPL");

2
drivers/clk/mediatek/clk-mt2701-img.c
View File

@ -54,4 +54,6 @@ static struct platform_driver clk_mt2701_img_drv = {
},
};
module_platform_driver(clk_mt2701_img_drv);
MODULE_DESCRIPTION("MediaTek MT2701 imgsys clocks driver");
MODULE_LICENSE("GPL");

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