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drm/i915/dp: Separate out function to get compressed bpp with joiner

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Pull the code to get joiner constraints on maximum compressed bpp into
separate function.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230817142459.89764-16-ankit.k.nautiyal@intel.com
This commit is contained in:
Ankit Nautiyal 2023-08-17 19:54:56 +05:30
parent 874aa4a3ff
commit a4d30841de
1 changed files with 30 additions and 24 deletions
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54
drivers/gpu/drm/i915/display/intel_dp.c
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@ -740,6 +740,32 @@ u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 p
return bits_per_pixel;
}
static
u32 get_max_compressed_bpp_with_joiner(struct drm_i915_private *i915,
u32 mode_clock, u32 mode_hdisplay,
bool bigjoiner)
{
u32 max_bpp_small_joiner_ram;
/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / mode_hdisplay;
if (bigjoiner) {
int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
/* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */
int ppc = 2;
u32 max_bpp_bigjoiner =
i915->display.cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits /
intel_dp_mode_to_fec_clock(mode_clock);
max_bpp_small_joiner_ram *= 2;
return min(max_bpp_small_joiner_ram, max_bpp_bigjoiner);
}
return max_bpp_small_joiner_ram;
}
u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
u32 link_clock, u32 lane_count,
u32 mode_clock, u32 mode_hdisplay,
@ -748,7 +774,7 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
u32 pipe_bpp,
u32 timeslots)
{
u32 bits_per_pixel, max_bpp_small_joiner_ram;
u32 bits_per_pixel, joiner_max_bpp;
/*
* Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
@ -788,29 +814,9 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915,
(link_clock * lane_count * 8),
intel_dp_mode_to_fec_clock(mode_clock));
/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
mode_hdisplay;
if (bigjoiner)
max_bpp_small_joiner_ram *= 2;
/*
* Greatest allowed DSC BPP = MIN (output BPP from available Link BW
* check, output bpp from small joiner RAM check)
*/
bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
if (bigjoiner) {
int bigjoiner_interface_bits = DISPLAY_VER(i915) >= 14 ? 36 : 24;
/* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */
int ppc = 2;
u32 max_bpp_bigjoiner =
i915->display.cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits /
intel_dp_mode_to_fec_clock(mode_clock);
bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
}
joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, mode_clock,
mode_hdisplay, bigjoiner);
bits_per_pixel = min(bits_per_pixel, joiner_max_bpp);
bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp);