Minki/linux
1
0
Fork 1
mirror of https://github.com/torvalds/linux.git synced 2024-11-23 12:42:02 +00:00
Code Issues Packages Projects Releases Wiki Activity

Fixes for ti81xx for v4.5 merge window. We have hp t410 already booting

Browse Source 
in mainline kernel with it's bootloader configured clocks.  However,
 trying to boot dm814x-evm uncovered all kind of issues with the timer
 clock. To keep t410 booting, these issues need to be fixed in a specific
 order and this branch contains both device tree and code changes.
 
 To summarize the changes, we had missing ranges for clocks to probe,
 missing aliase for clocks, wrong registers for divder clocks, and bad
 address for the control module. All these went unnoticed earlier as
 things worked without errors by luck and I did not pay much attention
 to them until I got hold of a dm814x-evm and I noticed it did not boot.
 
 As these are fixes for features that never worked, these can wait for
 v4.5 merge window no problem.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJWag8GAAoJEBvUPslcq6VzDmwP/3Zcu9WU4C/vTm3zig273PbV
 qmGMc5FshVmlInBEDE3FaCbE3EFscH1DfGP/rYV6e2bPZNl/NIhns0GlZdPA35TO
 TgXqijdoEOTqMHuCVQtkZkqPfCDR6JIGfnJ7Hk87gph/zDETRPBalAZKfqzsk2qg
 rAXOVCLCfhRqPO0Miav+VUS/7xZ8Qsz6ItnRmAr+dv95Wicq9OQoyG3Yrk3XEcDW
 PMnjoHCLaX9KdIyckLX9gWJP/qOL2eCHve45YliXxNYsh/h0CVSxqBkqhYydNgrm
 XqUOeRIja3pBV9ov3Y+jQn/9Y4cbKEkw168YQkMk5WNFbHZrAdV35e7JHpm6Q+un
 oH+w8UmncjwObYwkr6AmgOCTeuvAU76FtlPyD/Ct6oHk2hJjJ18AUCRgiUcZ5NEN
 Lx0NGWyZmNbMe7aqLHPEsrz+3SBir53xOFp8fElIvNM1eURP7nhBIX5SpNXjrZk1
 gpvlHROcZy2kYi5cjcBRHh4kZlHJuWFReLXj7L00YLAR67VHQeq8rZ212WZhef/o
 PGCBJonr1Tfhpe4iWRU4Z/Tm9c4DyO+yWQcHk/GjphACFEH37gdkH3Qzq4CFKz/6
 bQtKd4ky/0G965S2bFk5tljelU/+ro4jryE0yU3ip/5aSTlPb3LeZtd6+TzvUKg0
 96brOPxlxBBh/gQ0ExB6
 =Mesm
 -----END PGP SIGNATURE-----

Merge tag 'omap-for-v4.5/81xx-fixes-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/fixes-non-critical

Merge "omap fixes for 81xx for v4.5 merge window" from Tony Lindgren:

Fixes for ti81xx for v4.5 merge window. We have hp t410 already booting
in mainline kernel with it's bootloader configured clocks.  However,
trying to boot dm814x-evm uncovered all kind of issues with the timer
clock. To keep t410 booting, these issues need to be fixed in a specific
order and this branch contains both device tree and code changes.

To summarize the changes, we had missing ranges for clocks to probe,
missing aliase for clocks, wrong registers for divder clocks, and bad
address for the control module. All these went unnoticed earlier as
things worked without errors by luck and I did not pay much attention
to them until I got hold of a dm814x-evm and I noticed it did not boot.

As these are fixes for features that never worked, these can wait for
v4.5 merge window no problem.

* tag 'omap-for-v4.5/81xx-fixes-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP2+: Remove useless check for legacy booting for dm814x
  ARM: OMAP2+: Enable GPIO for dm814x
  ARM: dts: Fix dm814x pinctrl address and mask
  ARM: dts: Fix dm8148 control modules ranges
  ARM: OMAP2+: Fix timer entries for dm814x
  ARM: dts: Fix some mux and divider clocks to get dm814x-evm booting
  ARM: OMAP2+: Add DPPLS clock manager for dm814x
  clk: ti: Add few dm814x clock aliases
  ARM: dts: Fix dm814x entries for pllss and prcm
This commit is contained in:
Arnd Bergmann 2015-12-16 00:14:25 +01:00
commit a436848cc7
7 changed files with 124 additions and 48 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

113
arch/arm/boot/dts/dm814x-clocks.dtsi
View File

@ -4,18 +4,41 @@
* published by the Free Software Foundation.
*/
&scm_clocks {
tclkin_ck: tclkin_ck {
&pllss_clocks {
timer1_fck: timer1_fck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
compatible = "ti,mux-clock";
clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
&aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
ti,bit-shift = <3>;
reg = <0x2e0>;
};
timer2_fck: timer2_fck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
&aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
ti,bit-shift = <6>;
reg = <0x2e0>;
};
sysclk18_ck: sysclk18_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&rtcosc_ck>, <&rtcdivider_ck>;
ti,bit-shift = <0>;
reg = <0x02f0>;
};
};
&scm_clocks {
devosc_ck: devosc_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <20000000>;
compatible = "ti,mux-clock";
clocks = <&virt_20000000_ck>, <&virt_19200000_ck>;
ti,bit-shift = <21>;
reg = <0x0040>;
};
/* Optional auxosc, 20 - 30 MHz range, assume 27 MHz by default */
@ -25,6 +48,32 @@
clock-frequency = <27000000>;
};
/* Optional 32768Hz crystal or clock on RTCOSC pins */
rtcosc_ck: rtcosc_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
/* Optional external clock on TCLKIN pin, set rate in baord dts file */
tclkin_ck: tclkin_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
virt_20000000_ck: virt_20000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <20000000>;
};
virt_19200000_ck: virt_19200000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <19200000>;
};
mpu_ck: mpu_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
@ -49,12 +98,6 @@
clock-frequency = <48000000>;
};
sysclk18_ck: sysclk18_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
cpsw_125mhz_gclk: cpsw_125mhz_gclk {
#clock-cells = <0>;
compatible = "fixed-clock";
@ -69,7 +112,31 @@
};
&pllss_clocks {
&prcm_clocks {
osc_src_ck: osc_src_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&devosc_ck>;
clock-mult = <1>;
clock-div = <1>;
};
mpu_clksrc_ck: mpu_clksrc_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&devosc_ck>, <&rtcdivider_ck>;
ti,bit-shift = <0>;
reg = <0x0040>;
};
/* Fixed divider clock 0.0016384 * devosc */
rtcdivider_ck: rtcdivider_ck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&devosc_ck>;
clock-mult = <128>;
clock-div = <78125>;
};
aud_clkin0_ck: aud_clkin0_ck {
#clock-cells = <0>;
@ -88,22 +155,4 @@
compatible = "fixed-clock";
clock-frequency = <20000000>;
};
timer1_mux_ck: timer1_mux_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
&aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
ti,bit-shift = <3>;
reg = <0x2e0>;
};
timer2_mux_ck: timer2_mux_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
&aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
ti,bit-shift = <6>;
reg = <0x2e0>;
};
};

33
arch/arm/boot/dts/dm814x.dtsi
View File

@ -58,8 +58,10 @@
ti,hwmods = "l3_main";
/*
* See TRM "Table 1-317. L4LS Instance Summary", just deduct
* 0x1000 from the 1-317 addresses to get the device address
* See TRM "Table 1-317. L4LS Instance Summary" for hints.
* It shows the module target agent registers though, so the
* actual device is typically 0x1000 before the target agent
* except in cases where the module is larger than 0x1000.
*/
l4ls: l4ls@48000000 {
compatible = "ti,dm814-l4ls", "simple-bus";
@ -183,10 +185,10 @@
control: control@140000 {
compatible = "ti,dm814-scm", "simple-bus";
reg = <0x140000 0x16d000>;
reg = <0x140000 0x20000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x160000 0x16d000>;
ranges = <0 0x140000 0x20000>;
scm_conf: scm_conf@0 {
compatible = "syscon";
@ -203,19 +205,30 @@
};
};
/*
* Note that silicon revision 2.1 and older
* require input enabled (bit 18 set) for all
* 3.3V I/Os to avoid cumulative hardware damage.
* For more info, see errata advisory 2.1.87.
* We leave bit 18 out of function-mask and rely
* on the bootloader for it.
*/
pincntl: pinmux@800 {
compatible = "pinctrl-single";
reg = <0x800 0xc38>;
reg = <0x800 0x438>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x300ff>;
pinctrl-single,function-mask = <0x307ff>;
};
};
prcm: prcm@180000 {
compatible = "ti,dm814-prcm", "simple-bus";
reg = <0x180000 0x4000>;
reg = <0x180000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x180000 0x2000>;
prcm_clocks: clocks {
#address-cells = <1>;
@ -226,9 +239,13 @@
};
};
/* See TRM PLL_SUBSYS_BASE and "PLLSS Registers" */
pllss: pllss@1c5000 {
compatible = "ti,dm814-pllss", "simple-bus";
reg = <0x1c5000 0x2000>;
reg = <0x1c5000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1c5000 0x1000>;
pllss_clocks: clocks {
#address-cells = <1>;

3
arch/arm/mach-omap2/io.c
View File

@ -612,8 +612,7 @@ void __init ti814x_init_early(void)
ti814x_clockdomains_init();
dm814x_hwmod_init();
omap_hwmod_init_postsetup();
if (of_have_populated_dt())
omap_clk_soc_init = dm814x_dt_clk_init;
omap_clk_soc_init = dm814x_dt_clk_init;
}
void __init ti816x_init_early(void)

12
arch/arm/mach-omap2/omap_hwmod_81xx_data.c
View File

@ -599,7 +599,7 @@ static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
static struct omap_hwmod dm814x_timer1_hwmod = {
.name = "timer1",
.clkdm_name = "alwon_l3s_clkdm",
.main_clk = "timer_sys_ck",
.main_clk = "timer1_fck",
.dev_attr = &capability_alwon_dev_attr,
.class = &dm816x_timer_hwmod_class,
.flags = HWMOD_NO_IDLEST,
@ -608,7 +608,7 @@ static struct omap_hwmod dm814x_timer1_hwmod = {
static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = {
.master = &dm81xx_l4_ls_hwmod,
.slave = &dm814x_timer1_hwmod,
.clk = "timer_sys_ck",
.clk = "timer1_fck",
.user = OCP_USER_MPU,
};
@ -636,7 +636,7 @@ static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = {
static struct omap_hwmod dm814x_timer2_hwmod = {
.name = "timer2",
.clkdm_name = "alwon_l3s_clkdm",
.main_clk = "timer_sys_ck",
.main_clk = "timer2_fck",
.dev_attr = &capability_alwon_dev_attr,
.class = &dm816x_timer_hwmod_class,
.flags = HWMOD_NO_IDLEST,
@ -645,7 +645,7 @@ static struct omap_hwmod dm814x_timer2_hwmod = {
static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = {
.master = &dm81xx_l4_ls_hwmod,
.slave = &dm814x_timer2_hwmod,
.clk = "timer_sys_ck",
.clk = "timer2_fck",
.user = OCP_USER_MPU,
};
@ -1230,8 +1230,6 @@ static struct omap_hwmod_ocp_if dm81xx_tptc3__alwon_l3_fast = {
/*
* REVISIT: Test and enable the following once clocks work:
* dm81xx_l4_ls__gpio1
* dm81xx_l4_ls__gpio2
* dm81xx_l4_ls__mailbox
* dm81xx_alwon_l3_slow__gpmc
* dm81xx_default_l3_slow__usbss
@ -1250,6 +1248,8 @@ static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = {
&dm81xx_l4_ls__wd_timer1,
&dm81xx_l4_ls__i2c1,
&dm81xx_l4_ls__i2c2,
&dm81xx_l4_ls__gpio1,
&dm81xx_l4_ls__gpio2,
&dm81xx_l4_ls__elm,
&dm81xx_l4_ls__mcspi1,
&dm81xx_alwon_l3_fast__tpcc,

6
arch/arm/mach-omap2/prm_common.c
View File

@ -662,6 +662,11 @@ static struct omap_prcm_init_data am3_prm_data __initdata = {
.index = TI_CLKM_PRM,
.init = am33xx_prm_init,
};
static struct omap_prcm_init_data dm814_pllss_data __initdata = {
.index = TI_CLKM_PLLSS,
.init = am33xx_prm_init,
};
#endif
#ifdef CONFIG_ARCH_OMAP4
@ -715,6 +720,7 @@ static const struct of_device_id const omap_prcm_dt_match_table[] __initconst =
#endif
#ifdef CONFIG_SOC_TI81XX
{ .compatible = "ti,dm814-prcm", .data = &am3_prm_data },
{ .compatible = "ti,dm814-pllss", .data = &dm814_pllss_data },
{ .compatible = "ti,dm816-prcm", .data = &am3_prm_data },
#endif
#ifdef CONFIG_ARCH_OMAP2

4
drivers/clk/ti/clk-814x.c
View File

@ -14,10 +14,14 @@ static struct ti_dt_clk dm814_clks[] = {
DT_CLK(NULL, "devosc_ck", "devosc_ck"),
DT_CLK(NULL, "mpu_ck", "mpu_ck"),
DT_CLK(NULL, "sysclk4_ck", "sysclk4_ck"),
DT_CLK(NULL, "sysclk5_ck", "sysclk5_ck"),
DT_CLK(NULL, "sysclk6_ck", "sysclk6_ck"),
DT_CLK(NULL, "sysclk8_ck", "sysclk8_ck"),
DT_CLK(NULL, "sysclk10_ck", "sysclk10_ck"),
DT_CLK(NULL, "sysclk18_ck", "sysclk18_ck"),
DT_CLK(NULL, "timer_sys_ck", "devosc_ck"),
DT_CLK(NULL, "timer1_fck", "timer1_fck"),
DT_CLK(NULL, "timer2_fck", "timer2_fck"),
DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
{ .node_name = NULL },

1
include/linux/clk/ti.h
View File

@ -195,6 +195,7 @@ enum {
TI_CLKM_PRM,
TI_CLKM_SCRM,
TI_CLKM_CTRL,
TI_CLKM_PLLSS,
CLK_MAX_MEMMAPS
};