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clk: tegra: Export functions for EMC clock scaling

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Export functions to allow accessing the CAR register required by EMC
clock scaling. These functions will be used to access the CAR register
as part of the scaling sequence.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Joseph Lo 2019-05-29 16:21:34 +08:00 committed by Thierry Reding
parent cd4d6f3575
commit a3cba697a2
2 changed files with 29 additions and 0 deletions
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26
drivers/clk/tegra/clk-tegra210.c
View File

@ -37,6 +37,7 @@
#define CLK_SOURCE_LA 0x1f8
#define CLK_SOURCE_SDMMC2 0x154
#define CLK_SOURCE_SDMMC4 0x164
#define CLK_SOURCE_EMC_DLL 0x664
#define PLLC_BASE 0x80
#define PLLC_OUT 0x84
@ -227,6 +228,10 @@
#define RST_DFLL_DVCO 0x2f4
#define DVFS_DFLL_RESET_SHIFT 0
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_X_SET 0x284
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_X_CLR 0x288
#define CLK_OUT_ENB_X_CLK_ENB_EMC_DLL BIT(14)
#define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2a8
#define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2ac
#define CPU_SOFTRST_CTRL 0x380
@ -555,6 +560,27 @@ void tegra210_set_sata_pll_seq_sw(bool state)
}
EXPORT_SYMBOL_GPL(tegra210_set_sata_pll_seq_sw);
void tegra210_clk_emc_dll_enable(bool flag)
{
u32 offset = flag ? CLK_RST_CONTROLLER_CLK_OUT_ENB_X_SET :
CLK_RST_CONTROLLER_CLK_OUT_ENB_X_CLR;
writel_relaxed(CLK_OUT_ENB_X_CLK_ENB_EMC_DLL, clk_base + offset);
}
EXPORT_SYMBOL_GPL(tegra210_clk_emc_dll_enable);
void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value)
{
writel_relaxed(emc_dll_src_value, clk_base + CLK_SOURCE_EMC_DLL);
}
EXPORT_SYMBOL_GPL(tegra210_clk_emc_dll_update_setting);
void tegra210_clk_emc_update_setting(u32 emc_src_value)
{
writel_relaxed(emc_src_value, clk_base + CLK_SOURCE_EMC);
}
EXPORT_SYMBOL_GPL(tegra210_clk_emc_update_setting);
static void tegra210_generic_mbist_war(struct tegra210_domain_mbist_war *mbist)
{
u32 val;

3
include/linux/clk/tegra.h
View File

@ -131,6 +131,9 @@ extern void tegra210_set_sata_pll_seq_sw(bool state);
extern void tegra210_put_utmipll_in_iddq(void);
extern void tegra210_put_utmipll_out_iddq(void);
extern int tegra210_clk_handle_mbist_war(unsigned int id);
extern void tegra210_clk_emc_dll_enable(bool flag);
extern void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value);
extern void tegra210_clk_emc_update_setting(u32 emc_src_value);
struct clk;