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via-rhine: RHINE_WAIT_FOR macro removal.
Signed-off-by: Francois Romieu <romieu@fr.zoreil.com>
This commit is contained in:
parent
7ab87ff4c7
commit
a384a33bb1
@ -501,15 +501,31 @@ static int rhine_vlan_rx_add_vid(struct net_device *dev, unsigned short vid);
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static int rhine_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid);
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static void rhine_restart_tx(struct net_device *dev);
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#define RHINE_WAIT_FOR(condition) \
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do { \
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int i = 1024; \
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while (!(condition) && --i) \
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; \
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if (debug > 1 && i < 512) \
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pr_info("%4d cycles used @ %s:%d\n", \
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1024 - i, __func__, __LINE__); \
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} while (0)
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static void rhine_wait_bit(struct rhine_private *rp, u8 reg, u8 mask, bool high)
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{
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void __iomem *ioaddr = rp->base;
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int i;
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for (i = 0; i < 1024; i++) {
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if (high ^ !!(ioread8(ioaddr + reg) & mask))
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break;
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udelay(10);
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}
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if (i > 64) {
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netdev_dbg(rp->dev, "%s bit wait (%02x/%02x) cycle "
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"count: %04d\n", high ? "high" : "low", reg, mask, i);
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}
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}
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static void rhine_wait_bit_high(struct rhine_private *rp, u8 reg, u8 mask)
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{
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rhine_wait_bit(rp, reg, mask, true);
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}
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static void rhine_wait_bit_low(struct rhine_private *rp, u8 reg, u8 mask)
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{
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rhine_wait_bit(rp, reg, mask, false);
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}
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static u32 rhine_get_events(struct rhine_private *rp)
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{
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@ -609,7 +625,7 @@ static void rhine_chip_reset(struct net_device *dev)
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iowrite8(0x40, ioaddr + MiscCmd);
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/* Reset can take somewhat longer (rare) */
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RHINE_WAIT_FOR(!(ioread8(ioaddr + ChipCmd1) & Cmd1Reset));
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rhine_wait_bit_low(rp, ChipCmd1, Cmd1Reset);
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}
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if (debug > 1)
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@ -641,9 +657,15 @@ static void __devinit rhine_reload_eeprom(long pioaddr, struct net_device *dev)
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{
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struct rhine_private *rp = netdev_priv(dev);
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void __iomem *ioaddr = rp->base;
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int i;
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outb(0x20, pioaddr + MACRegEEcsr);
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RHINE_WAIT_FOR(!(inb(pioaddr + MACRegEEcsr) & 0x20));
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for (i = 0; i < 1024; i++) {
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if (!(inb(pioaddr + MACRegEEcsr) & 0x20))
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break;
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}
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if (i > 512)
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pr_info("%4d cycles used @ %s:%d\n", i, __func__, __LINE__);
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#ifdef USE_MMIO
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/*
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@ -770,7 +792,7 @@ static int rhine_napipoll(struct napi_struct *napi, int budget)
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u8 cmd;
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/* Avoid scavenging before Tx engine turned off */
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RHINE_WAIT_FOR(!(ioread8(ioaddr + ChipCmd) & CmdTxOn));
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rhine_wait_bit_low(rp, ChipCmd, CmdTxOn);
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cmd = ioread8(ioaddr + ChipCmd);
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if ((cmd & CmdTxOn) && (debug > 2)) {
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netdev_warn(dev, "%s: Tx engine still on\n",
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@ -1444,23 +1466,27 @@ static void init_registers(struct net_device *dev)
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}
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/* Enable MII link status auto-polling (required for IntrLinkChange) */
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static void rhine_enable_linkmon(void __iomem *ioaddr)
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static void rhine_enable_linkmon(struct rhine_private *rp)
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{
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void __iomem *ioaddr = rp->base;
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iowrite8(0, ioaddr + MIICmd);
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iowrite8(MII_BMSR, ioaddr + MIIRegAddr);
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iowrite8(0x80, ioaddr + MIICmd);
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RHINE_WAIT_FOR((ioread8(ioaddr + MIIRegAddr) & 0x20));
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rhine_wait_bit_high(rp, MIIRegAddr, 0x20);
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iowrite8(MII_BMSR | 0x40, ioaddr + MIIRegAddr);
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}
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/* Disable MII link status auto-polling (required for MDIO access) */
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static void rhine_disable_linkmon(void __iomem *ioaddr, u32 quirks)
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static void rhine_disable_linkmon(struct rhine_private *rp)
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{
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void __iomem *ioaddr = rp->base;
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iowrite8(0, ioaddr + MIICmd);
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if (quirks & rqRhineI) {
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if (rp->quirks & rqRhineI) {
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iowrite8(0x01, ioaddr + MIIRegAddr); // MII_BMSR
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/* Can be called from ISR. Evil. */
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@ -1469,13 +1495,13 @@ static void rhine_disable_linkmon(void __iomem *ioaddr, u32 quirks)
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/* 0x80 must be set immediately before turning it off */
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iowrite8(0x80, ioaddr + MIICmd);
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RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x20);
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rhine_wait_bit_high(rp, MIIRegAddr, 0x20);
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/* Heh. Now clear 0x80 again. */
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iowrite8(0, ioaddr + MIICmd);
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}
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else
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RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x80);
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rhine_wait_bit_high(rp, MIIRegAddr, 0x80);
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}
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/* Read and write over the MII Management Data I/O (MDIO) interface. */
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@ -1486,16 +1512,16 @@ static int mdio_read(struct net_device *dev, int phy_id, int regnum)
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void __iomem *ioaddr = rp->base;
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int result;
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rhine_disable_linkmon(ioaddr, rp->quirks);
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rhine_disable_linkmon(rp);
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/* rhine_disable_linkmon already cleared MIICmd */
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iowrite8(phy_id, ioaddr + MIIPhyAddr);
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iowrite8(regnum, ioaddr + MIIRegAddr);
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iowrite8(0x40, ioaddr + MIICmd); /* Trigger read */
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RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x40));
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rhine_wait_bit_low(rp, MIICmd, 0x40);
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result = ioread16(ioaddr + MIIData);
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rhine_enable_linkmon(ioaddr);
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rhine_enable_linkmon(rp);
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return result;
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}
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@ -1504,16 +1530,16 @@ static void mdio_write(struct net_device *dev, int phy_id, int regnum, int value
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struct rhine_private *rp = netdev_priv(dev);
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void __iomem *ioaddr = rp->base;
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rhine_disable_linkmon(ioaddr, rp->quirks);
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rhine_disable_linkmon(rp);
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/* rhine_disable_linkmon already cleared MIICmd */
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iowrite8(phy_id, ioaddr + MIIPhyAddr);
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iowrite8(regnum, ioaddr + MIIRegAddr);
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iowrite16(value, ioaddr + MIIData);
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iowrite8(0x20, ioaddr + MIICmd); /* Trigger write */
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RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x20));
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rhine_wait_bit_low(rp, MIICmd, 0x20);
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rhine_enable_linkmon(ioaddr);
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rhine_enable_linkmon(rp);
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}
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static void rhine_task_disable(struct rhine_private *rp)
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