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ath10k: add QCA9377 chipset support
Add the hardware name, revision and update the pci_id table. Currently there're two HW ref. designs available I'm aware of, with 1.0.2 and 1.1 chip revisions. I've access and been using the first one so far and this patch cover only it. QCA9377 inherits most of the stuff (e.g. fw interfaces) from QCA61x4 design, so the integration was pretty straightforward. Signed-off-by: Bartosz Markowski <bartosz.markowski@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
This commit is contained in:
Bartosz Markowski
Kalle Valo
parent
5036fe0f6f
commit
a226b519d4
@ -137,6 +137,21 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
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},
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},
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{
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.id = QCA9377_HW_1_0_DEV_VERSION,
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.name = "qca9377 hw1.0",
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.patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
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.uart_pin = 7,
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.otp_exe_param = 0,
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.fw = {
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.dir = QCA9377_HW_1_0_FW_DIR,
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.fw = QCA9377_HW_1_0_FW_FILE,
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.otp = QCA9377_HW_1_0_OTP_FILE,
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.board = QCA9377_HW_1_0_BOARD_DATA_FILE,
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.board_size = QCA9377_BOARD_DATA_SZ,
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.board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
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},
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},
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};
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static const char *const ath10k_core_fw_feature_str[] = {
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@ -1901,6 +1916,7 @@ struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
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ar->hw_values = &qca988x_values;
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break;
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case ATH10K_HW_QCA6174:
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case ATH10K_HW_QCA9377:
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ar->regs = &qca6174_regs;
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ar->hw_values = &qca6174_values;
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break;
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@ -84,6 +84,15 @@ enum qca6174_chip_id_rev {
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#define QCA99X0_HW_2_0_BOARD_DATA_FILE "board.bin"
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#define QCA99X0_HW_2_0_PATCH_LOAD_ADDR 0x1234
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/* QCA9377 1.0 definitions */
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#define QCA9377_HW_1_0_DEV_VERSION 0x05020001
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#define QCA9377_HW_1_0_CHIP_ID_REV 0x1
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#define QCA9377_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9377/hw1.0"
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#define QCA9377_HW_1_0_FW_FILE "firmware.bin"
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#define QCA9377_HW_1_0_OTP_FILE "otp.bin"
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#define QCA9377_HW_1_0_BOARD_DATA_FILE "board.bin"
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#define QCA9377_HW_1_0_PATCH_LOAD_ADDR 0x1234
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#define ATH10K_FW_API2_FILE "firmware-2.bin"
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#define ATH10K_FW_API3_FILE "firmware-3.bin"
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@ -177,6 +186,7 @@ enum ath10k_hw_rev {
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ATH10K_HW_QCA988X,
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ATH10K_HW_QCA6174,
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ATH10K_HW_QCA99X0,
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ATH10K_HW_QCA9377,
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};
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struct ath10k_hw_regs {
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@ -229,6 +239,7 @@ void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
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#define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X)
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#define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174)
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#define QCA_REV_99X0(ar) ((ar)->hw_rev == ATH10K_HW_QCA99X0)
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#define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377)
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/* Known pecularities:
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* - raw appears in nwifi decap, raw and nwifi appear in ethernet decap
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@ -61,12 +61,14 @@ MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)");
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#define QCA6164_2_1_DEVICE_ID (0x0041)
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#define QCA6174_2_1_DEVICE_ID (0x003e)
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#define QCA99X0_2_0_DEVICE_ID (0x0040)
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#define QCA9377_1_0_DEVICE_ID (0x0042)
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static const struct pci_device_id ath10k_pci_id_table[] = {
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{ PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
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{ PCI_VDEVICE(ATHEROS, QCA6164_2_1_DEVICE_ID) }, /* PCI-E QCA6164 V2.1 */
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{ PCI_VDEVICE(ATHEROS, QCA6174_2_1_DEVICE_ID) }, /* PCI-E QCA6174 V2.1 */
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{ PCI_VDEVICE(ATHEROS, QCA99X0_2_0_DEVICE_ID) }, /* PCI-E QCA99X0 V2 */
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{ PCI_VDEVICE(ATHEROS, QCA9377_1_0_DEVICE_ID) }, /* PCI-E QCA9377 V1 */
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{0}
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};
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@ -90,6 +92,7 @@ static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips[] = {
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{ QCA6174_2_1_DEVICE_ID, QCA6174_HW_3_2_CHIP_ID_REV },
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{ QCA99X0_2_0_DEVICE_ID, QCA99X0_HW_2_0_CHIP_ID_REV },
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{ QCA9377_1_0_DEVICE_ID, QCA9377_HW_1_0_CHIP_ID_REV },
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};
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static void ath10k_pci_buffer_cleanup(struct ath10k *ar);
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@ -827,6 +830,7 @@ static u32 ath10k_pci_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
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switch (ar->hw_rev) {
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case ATH10K_HW_QCA988X:
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case ATH10K_HW_QCA6174:
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case ATH10K_HW_QCA9377:
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val = (ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
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CORE_CTRL_ADDRESS) &
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0x7ff) << 21;
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@ -1483,6 +1487,7 @@ static void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar)
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switch (ar->hw_rev) {
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case ATH10K_HW_QCA988X:
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case ATH10K_HW_QCA6174:
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case ATH10K_HW_QCA9377:
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val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
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CORE_CTRL_ADDRESS);
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val &= ~CORE_CTRL_PCIE_REG_31_MASK;
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@ -1504,6 +1509,7 @@ static void ath10k_pci_irq_msi_fw_unmask(struct ath10k *ar)
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switch (ar->hw_rev) {
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case ATH10K_HW_QCA988X:
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case ATH10K_HW_QCA6174:
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case ATH10K_HW_QCA9377:
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val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
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CORE_CTRL_ADDRESS);
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val |= CORE_CTRL_PCIE_REG_31_MASK;
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@ -1872,6 +1878,8 @@ static int ath10k_pci_get_num_banks(struct ath10k *ar)
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return 9;
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}
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break;
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case QCA9377_1_0_DEVICE_ID:
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return 2;
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}
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ath10k_warn(ar, "unknown number of banks, assuming 1\n");
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@ -2332,6 +2340,8 @@ static int ath10k_pci_chip_reset(struct ath10k *ar)
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return ath10k_pci_qca988x_chip_reset(ar);
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else if (QCA_REV_6174(ar))
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return ath10k_pci_qca6174_chip_reset(ar);
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else if (QCA_REV_9377(ar))
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return ath10k_pci_qca6174_chip_reset(ar);
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else if (QCA_REV_99X0(ar))
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return ath10k_pci_qca99x0_chip_reset(ar);
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else
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@ -2964,6 +2974,10 @@ static int ath10k_pci_probe(struct pci_dev *pdev,
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hw_rev = ATH10K_HW_QCA99X0;
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pci_ps = false;
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break;
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case QCA9377_1_0_DEVICE_ID:
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hw_rev = ATH10K_HW_QCA9377;
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pci_ps = true;
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break;
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default:
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WARN_ON(1);
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return -ENOTSUPP;
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@ -3165,3 +3179,7 @@ MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API4_FILE);
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MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_FW_API5_FILE);
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MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" QCA6174_HW_3_0_BOARD_DATA_FILE);
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MODULE_FIRMWARE(QCA6174_HW_3_0_FW_DIR "/" ATH10K_BOARD_API2_FILE);
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/* QCA9377 1.0 firmware files */
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MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" ATH10K_FW_API5_FILE);
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MODULE_FIRMWARE(QCA9377_HW_1_0_FW_DIR "/" QCA9377_HW_1_0_BOARD_DATA_FILE);
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@ -450,6 +450,9 @@ Fw Mode/SubMode Mask
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#define QCA6174_BOARD_DATA_SZ 8192
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#define QCA6174_BOARD_EXT_DATA_SZ 0
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#define QCA9377_BOARD_DATA_SZ QCA6174_BOARD_DATA_SZ
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#define QCA9377_BOARD_EXT_DATA_SZ 0
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#define QCA99X0_BOARD_DATA_SZ 12288
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#define QCA99X0_BOARD_EXT_DATA_SZ 0
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