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arm/imx6q: add suspend/resume support
It adds suspend/resume support for imx6q. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This commit is contained in:
Shawn Guo
Arnd Bergmann
parent
13eed9897a
commit
a1f1c7efb0
@ -70,4 +70,4 @@ AFLAGS_head-v7.o :=-Wa,-march=armv7-a
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obj-$(CONFIG_SMP) += platsmp.o
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obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
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obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
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obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o
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obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o pm-imx6q.o
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@ -12,6 +12,7 @@
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/asm-offsets.h>
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#include <asm/hardware/cache-l2x0.h>
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.section ".text.head", "ax"
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@ -69,3 +70,30 @@ ENTRY(v7_secondary_startup)
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b secondary_startup
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ENDPROC(v7_secondary_startup)
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#endif
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/*
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* The following code is located into the .data section. This is to
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* allow phys_l2x0_saved_regs to be accessed with a relative load
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* as we are running on physical address here.
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*/
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.data
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.align
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.macro pl310_resume
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ldr r2, phys_l2x0_saved_regs
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ldr r0, [r2, #L2X0_R_PHY_BASE] @ get physical base of l2x0
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ldr r1, [r2, #L2X0_R_AUX_CTRL] @ get aux_ctrl value
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str r1, [r0, #L2X0_AUX_CTRL] @ restore aux_ctrl
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mov r1, #0x1
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str r1, [r0, #L2X0_CTRL] @ re-enable L2
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.endm
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ENTRY(v7_cpu_resume)
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bl v7_invalidate_l1
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pl310_resume
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b cpu_resume
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ENDPROC(v7_cpu_resume)
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.globl phys_l2x0_saved_regs
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phys_l2x0_saved_regs:
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.long 0
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70
arch/arm/mach-imx/pm-imx6q.c
Normal file
70
arch/arm/mach-imx/pm-imx6q.c
Normal file
@ -0,0 +1,70 @@
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/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/suspend.h>
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#include <asm/cacheflush.h>
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#include <asm/proc-fns.h>
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#include <asm/suspend.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <mach/common.h>
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#include <mach/hardware.h>
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extern unsigned long phys_l2x0_saved_regs;
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static int imx6q_suspend_finish(unsigned long val)
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{
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cpu_do_idle();
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return 0;
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}
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static int imx6q_pm_enter(suspend_state_t state)
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{
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switch (state) {
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case PM_SUSPEND_MEM:
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imx6q_set_lpm(STOP_POWER_OFF);
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imx_gpc_pre_suspend();
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imx_set_cpu_jump(0, v7_cpu_resume);
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/* Zzz ... */
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cpu_suspend(0, imx6q_suspend_finish);
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imx_smp_prepare();
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imx_gpc_post_resume();
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static const struct platform_suspend_ops imx6q_pm_ops = {
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.enter = imx6q_pm_enter,
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.valid = suspend_valid_only_mem,
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};
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void __init imx6q_pm_init(void)
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{
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/*
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* The l2x0 core code provides an infrastucture to save and restore
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* l2x0 registers across suspend/resume cycle. But because imx6q
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* retains L2 content during suspend and needs to resume L2 before
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* MMU is enabled, it can only utilize register saving support and
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* have to take care of restoring on its own. So we save physical
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* address of the data structure used by l2x0 core to save registers,
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* and later restore the necessary ones in imx6q resume entry.
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*/
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phys_l2x0_saved_regs = __pa(&l2x0_saved_regs);
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suspend_set_ops(&imx6q_pm_ops);
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}
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@ -13,6 +13,7 @@
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struct platform_device;
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struct clk;
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enum mxc_cpu_pwr_mode;
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extern void mx1_map_io(void);
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extern void mx21_map_io(void);
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@ -107,14 +108,22 @@ extern void imx_lluart_map_io(void);
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#else
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static inline void imx_lluart_map_io(void) {}
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#endif
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extern void v7_cpu_resume(void);
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extern u32 *pl310_get_save_ptr(void);
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#ifdef CONFIG_SMP
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extern void v7_secondary_startup(void);
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extern void imx_scu_map_io(void);
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extern void imx_smp_prepare(void);
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#else
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static inline void imx_scu_map_io(void) {}
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static inline void imx_smp_prepare(void) {}
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#endif
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extern void imx_enable_cpu(int cpu, bool enable);
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extern void imx_set_cpu_jump(int cpu, void *jump_addr);
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extern void imx_src_init(void);
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extern void imx_gpc_init(void);
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extern void imx_gpc_pre_suspend(void);
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extern void imx_gpc_post_resume(void);
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extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
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extern void imx6q_pm_init(void);
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#endif
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