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powerpc/mpc5200: add PSC SICR bit definitions
Required by the PSC I2S audio driver. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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@ -60,10 +60,12 @@
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#define MPC52xx_PSC_RXTX_FIFO_ALARM 0x0002
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#define MPC52xx_PSC_RXTX_FIFO_EMPTY 0x0001
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/* PSC interrupt mask bits */
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/* PSC interrupt status/mask bits */
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#define MPC52xx_PSC_IMR_TXRDY 0x0100
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#define MPC52xx_PSC_IMR_RXRDY 0x0200
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#define MPC52xx_PSC_IMR_DB 0x0400
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#define MPC52xx_PSC_IMR_TXEMP 0x0800
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#define MPC52xx_PSC_IMR_ORERR 0x1000
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#define MPC52xx_PSC_IMR_IPC 0x8000
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/* PSC input port change bit */
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@ -92,6 +94,34 @@
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#define MPC52xx_PSC_RFNUM_MASK 0x01ff
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#define MPC52xx_PSC_SICR_DTS1 (1 << 29)
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#define MPC52xx_PSC_SICR_SHDR (1 << 28)
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#define MPC52xx_PSC_SICR_SIM_MASK (0xf << 24)
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#define MPC52xx_PSC_SICR_SIM_UART (0x0 << 24)
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#define MPC52xx_PSC_SICR_SIM_UART_DCD (0x8 << 24)
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#define MPC52xx_PSC_SICR_SIM_CODEC_8 (0x1 << 24)
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#define MPC52xx_PSC_SICR_SIM_CODEC_16 (0x2 << 24)
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#define MPC52xx_PSC_SICR_SIM_AC97 (0x3 << 24)
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#define MPC52xx_PSC_SICR_SIM_SIR (0x8 << 24)
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#define MPC52xx_PSC_SICR_SIM_SIR_DCD (0xc << 24)
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#define MPC52xx_PSC_SICR_SIM_MIR (0x5 << 24)
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#define MPC52xx_PSC_SICR_SIM_FIR (0x6 << 24)
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#define MPC52xx_PSC_SICR_SIM_CODEC_24 (0x7 << 24)
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#define MPC52xx_PSC_SICR_SIM_CODEC_32 (0xf << 24)
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#define MPC52xx_PSC_SICR_GENCLK (1 << 23)
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#define MPC52xx_PSC_SICR_I2S (1 << 22)
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#define MPC52xx_PSC_SICR_CLKPOL (1 << 21)
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#define MPC52xx_PSC_SICR_SYNCPOL (1 << 20)
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#define MPC52xx_PSC_SICR_CELLSLAVE (1 << 19)
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#define MPC52xx_PSC_SICR_CELL2XCLK (1 << 18)
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#define MPC52xx_PSC_SICR_ESAI (1 << 17)
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#define MPC52xx_PSC_SICR_ENAC97 (1 << 16)
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#define MPC52xx_PSC_SICR_SPI (1 << 15)
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#define MPC52xx_PSC_SICR_MSTR (1 << 14)
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#define MPC52xx_PSC_SICR_CPOL (1 << 13)
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#define MPC52xx_PSC_SICR_CPHA (1 << 12)
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#define MPC52xx_PSC_SICR_USEEOF (1 << 11)
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#define MPC52xx_PSC_SICR_DISABLEEOF (1 << 10)
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/* Structure of the hardware registers */
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struct mpc52xx_psc {
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