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firewire: OHCI 1.0 Isochronous Receive support
Third rendition of FireWire OHCI 1.0 Isochronous Receive support, using a zer-copy method similar to OHCI 1.1 which puts the IR data payload directly into the userspace buffer. The zero-copy implementation eliminates the video artifacts, audio popping, and buffer underrun problems seen with version 1 of this patch, as well as fixing a regression in OHCI 1.1 support introduced by version 2 of this patch. Successfully tested in OHCI 1.1 mode on the following chipsets: - NEC uPD72847 (rev 01), OHCI 1.1 (PCI) - Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe) - Ti TSB41AB2 (rev 01), OHCI 1.1 (PCI on SB Audigy) - Apple UniNorth 2 (rev 81), OHCI 1.1 (PowerBook G4 onboard) Successfully tested in OHCI 1.0 mode on the following chipsets: - Agere FW323 (rev 06), OHCI 1.0 (Mac Mini onboard) - Agere FW323 (rev 06), OHCI 1.0 (PCI) - Via VT6306 (rev 46), OHCI 1.0 (PCI) - NEC OrangeLink (rev 01), OHCI 1.0 (PCI) - NEC uPD72847 (rev 01), OHCI 1.1 (PCI) - Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe) The bulk of testing was done in an x86_64 system, but was also successfully sanity-tested on other systems, including a PPC(32) PowerBook G4 and an i686 EPIA M10k. Crude benchmarking (watching top during capture) puts the cpu utilization during capture on the EPIA's 1GHz Via C3 processor around 13%, which is down from 30% with the v1 code. Some implementation details: To maintain the same userspace API as dual-buffer mode, we set up two descriptors for every incoming packet. The first is an INPUT_MORE descriptor, pointing to a buffer large enough to hold just the packet's iso headers, immediately followed by an INPUT_LAST descriptor, pointing to a chunk of the userspace buffer big enough for the packet's data payload. With this setup, each incoming packet fills in these two descriptors in a manner that very closely emulates dual-buffer receive, to the point where the bulk of the handle_ir_* code is now identical between the two (and probably primed for some restructuring to share code between them). The only caveat I have at the moment is that neither of my OHCI 1.0 Via VT6307-based FireWire controllers work particularly well with this code for reasons I have yet to figure out. Signed-off-by: Jarod Wilson <jwilson@redhat.com> Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
This commit is contained in:
Jarod Wilson
Stefan Richter
parent
41f81e88e0
commit
a186b4a6b2
@ -437,6 +437,21 @@ static void ar_context_run(struct ar_context *ctx)
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flush_writes(ctx->ohci);
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}
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static struct descriptor *
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find_branch_descriptor(struct descriptor *d, int z)
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{
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int b, key;
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b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
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key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
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/* figure out which descriptor the branch address goes in */
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if (z == 2 && (b == 3 || key == 2))
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return d;
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else
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return d + z - 1;
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}
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static void context_tasklet(unsigned long data)
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{
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struct context *ctx = (struct context *) data;
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@ -455,7 +470,7 @@ static void context_tasklet(unsigned long data)
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address = le32_to_cpu(last->branch_address);
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z = address & 0xf;
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d = ctx->buffer + (address - ctx->buffer_bus) / sizeof(*d);
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last = (z == 2) ? d : d + z - 1;
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last = find_branch_descriptor(d, z);
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if (!ctx->callback(ctx, d, last))
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break;
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@ -566,7 +581,7 @@ static void context_append(struct context *ctx,
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ctx->head_descriptor = d + z + extra;
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ctx->prev_descriptor->branch_address = cpu_to_le32(d_bus | z);
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ctx->prev_descriptor = z == 2 ? d : d + z - 1;
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ctx->prev_descriptor = find_branch_descriptor(d, z);
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dma_sync_single_for_device(ctx->ohci->card.device, ctx->buffer_bus,
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ctx->buffer_size, DMA_TO_DEVICE);
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@ -655,7 +670,7 @@ at_context_queue_packet(struct context *ctx, struct fw_packet *packet)
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driver_data = (struct driver_data *) &d[3];
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driver_data->packet = packet;
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packet->driver_data = driver_data;
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if (packet->payload_length > 0) {
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payload_bus =
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dma_map_single(ohci->card.device, packet->payload,
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@ -903,7 +918,7 @@ at_context_transmit(struct context *ctx, struct fw_packet *packet)
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if (retval < 0)
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packet->callback(packet, &ctx->ohci->card, packet->ack);
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}
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static void bus_reset_tasklet(unsigned long data)
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@ -1431,6 +1446,57 @@ static int handle_ir_dualbuffer_packet(struct context *context,
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return 1;
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}
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static int handle_ir_packet_per_buffer(struct context *context,
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struct descriptor *d,
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struct descriptor *last)
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{
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struct iso_context *ctx =
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container_of(context, struct iso_context, context);
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struct descriptor *pd = d + 1;
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__le32 *ir_header;
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size_t header_length;
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void *p, *end;
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int i, z;
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if (pd->res_count == pd->req_count)
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/* Descriptor(s) not done yet, stop iteration */
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return 0;
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header_length = le16_to_cpu(d->req_count);
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i = ctx->header_length;
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z = le32_to_cpu(pd->branch_address) & 0xf;
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p = d + z;
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end = p + header_length;
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while (p < end && i + ctx->base.header_size <= PAGE_SIZE) {
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/*
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* The iso header is byteswapped to little endian by
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* the controller, but the remaining header quadlets
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* are big endian. We want to present all the headers
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* as big endian, so we have to swap the first quadlet.
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*/
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*(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
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memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
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i += ctx->base.header_size;
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p += ctx->base.header_size + 4;
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}
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ctx->header_length = i;
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if (le16_to_cpu(pd->control) & DESCRIPTOR_IRQ_ALWAYS) {
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ir_header = (__le32 *) (d + z);
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ctx->base.callback(&ctx->base,
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le32_to_cpu(ir_header[0]) & 0xffff,
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ctx->header_length, ctx->header,
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ctx->base.callback_data);
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ctx->header_length = 0;
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}
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return 1;
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}
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static int handle_it_packet(struct context *context,
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struct descriptor *d,
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struct descriptor *last)
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@ -1466,14 +1532,12 @@ ohci_allocate_iso_context(struct fw_card *card, int type, size_t header_size)
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} else {
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mask = &ohci->ir_context_mask;
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list = ohci->ir_context_list;
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callback = handle_ir_dualbuffer_packet;
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if (ohci->version >= OHCI_VERSION_1_1)
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callback = handle_ir_dualbuffer_packet;
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else
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callback = handle_ir_packet_per_buffer;
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}
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/* FIXME: We need a fallback for pre 1.1 OHCI. */
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if (callback == handle_ir_dualbuffer_packet &&
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ohci->version < OHCI_VERSION_1_1)
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return ERR_PTR(-ENOSYS);
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spin_lock_irqsave(&ohci->lock, flags);
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index = ffs(*mask) - 1;
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if (index >= 0)
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@ -1532,7 +1596,9 @@ static int ohci_start_iso(struct fw_iso_context *base,
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context_run(&ctx->context, match);
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} else {
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index = ctx - ohci->ir_context_list;
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control = IR_CONTEXT_DUAL_BUFFER_MODE | IR_CONTEXT_ISOCH_HEADER;
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control = IR_CONTEXT_ISOCH_HEADER;
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if (ohci->version >= OHCI_VERSION_1_1)
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control |= IR_CONTEXT_DUAL_BUFFER_MODE;
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match = (tags << 28) | (sync << 8) | ctx->base.channel;
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if (cycle >= 0) {
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match |= (cycle & 0x07fff) << 12;
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@ -1738,7 +1804,6 @@ ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
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offset = payload & ~PAGE_MASK;
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rest = p->payload_length;
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/* FIXME: OHCI 1.0 doesn't support dual buffer receive */
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/* FIXME: make packet-per-buffer/dual-buffer a context option */
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while (rest > 0) {
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d = context_get_descriptors(&ctx->context,
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@ -1776,6 +1841,81 @@ ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
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return 0;
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}
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static int
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ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
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struct fw_iso_packet *packet,
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struct fw_iso_buffer *buffer,
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unsigned long payload)
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{
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struct iso_context *ctx = container_of(base, struct iso_context, base);
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struct descriptor *d = NULL, *pd = NULL;
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struct fw_iso_packet *p;
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dma_addr_t d_bus, page_bus;
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u32 z, header_z, rest;
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int i, page, offset, packet_count, header_size;
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if (packet->skip) {
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d = context_get_descriptors(&ctx->context, 1, &d_bus);
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if (d == NULL)
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return -ENOMEM;
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d->control = cpu_to_le16(DESCRIPTOR_STATUS |
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DESCRIPTOR_INPUT_LAST |
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DESCRIPTOR_BRANCH_ALWAYS |
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DESCRIPTOR_WAIT);
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context_append(&ctx->context, d, 1, 0);
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}
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/* one descriptor for header, one for payload */
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/* FIXME: handle cases where we need multiple desc. for payload */
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z = 2;
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p = packet;
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/*
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* The OHCI controller puts the status word in the
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* buffer too, so we need 4 extra bytes per packet.
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*/
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packet_count = p->header_length / ctx->base.header_size;
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header_size = packet_count * (ctx->base.header_size + 4);
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/* Get header size in number of descriptors. */
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header_z = DIV_ROUND_UP(header_size, sizeof(*d));
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page = payload >> PAGE_SHIFT;
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offset = payload & ~PAGE_MASK;
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rest = p->payload_length;
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for (i = 0; i < packet_count; i++) {
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/* d points to the header descriptor */
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d = context_get_descriptors(&ctx->context,
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z + header_z, &d_bus);
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if (d == NULL)
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return -ENOMEM;
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d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE);
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d->req_count = cpu_to_le16(header_size);
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d->res_count = d->req_count;
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d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
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/* pd points to the payload descriptor */
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pd = d + 1;
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pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
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DESCRIPTOR_INPUT_LAST |
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DESCRIPTOR_BRANCH_ALWAYS);
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if (p->interrupt)
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pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
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pd->req_count = cpu_to_le16(rest);
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pd->res_count = pd->req_count;
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page_bus = page_private(buffer->pages[page]);
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pd->data_address = cpu_to_le32(page_bus + offset);
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context_append(&ctx->context, d, z, header_z);
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}
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return 0;
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}
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static int
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ohci_queue_iso(struct fw_iso_context *base,
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struct fw_iso_packet *packet,
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@ -1790,8 +1930,9 @@ ohci_queue_iso(struct fw_iso_context *base,
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return ohci_queue_iso_receive_dualbuffer(base, packet,
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buffer, payload);
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else
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/* FIXME: Implement fallback for OHCI 1.0 controllers. */
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return -ENOSYS;
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return ohci_queue_iso_receive_packet_per_buffer(base, packet,
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buffer,
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payload);
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}
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static const struct fw_card_driver ohci_driver = {
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@ -1911,12 +2052,6 @@ pci_probe(struct pci_dev *dev, const struct pci_device_id *ent)
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ohci->version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
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fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
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dev->dev.bus_id, ohci->version >> 16, ohci->version & 0xff);
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if (ohci->version < OHCI_VERSION_1_1) {
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fw_notify(" Isochronous I/O is not yet implemented for "
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"OHCI 1.0 chips.\n");
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fw_notify(" Cameras, audio devices etc. won't work on "
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"this controller with this driver version.\n");
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}
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return 0;
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fail_self_id:
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