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serial: 8250_lpss: split LPSS driver to separate module
The SoCs, such as Intel Braswell, have DesignWare UART IP. Split out the support of such chips to a separate module which also will be used for Intel Quark later. The rationale to have the separate driver to be existing: - Do not contaminate 8250_pci.c anymore with LPSS related quirks - All of them are using same DMA engine and they are Designware IP which means that in the future we might share the code between 8250_dw.c and 8250_lpss.c - It reduces the kernel memory footprint on non-X86 machines where 8250_pci.c is in use Besides the split the driver also has been refactored, in particular a) the DMA and port setup are separate functions, b) the two new structures lpss8250 and lpss8250_board are introduced to keep necessary data instead of pciserial_board, c) DMA parameters are passed to the DMA setup via mentioned custom structure. Most of the changes are done due to the future support of UART DMA on Intel Quark. The Intel Quark UART DMA support is based on bits taking from BSP code published by Intel earlier. The driver does not use any specific power management. PCI core takes care of the default behaviour during suspend and resume. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Bryan O'Donoghue <pure.logic@nexus-software.ie> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Andy Shevchenko
Greg Kroah-Hartman
parent
68af490b03
commit
a13e19cf3d
280
drivers/tty/serial/8250/8250_lpss.c
Normal file
280
drivers/tty/serial/8250/8250_lpss.c
Normal file
@ -0,0 +1,280 @@
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/*
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* 8250_lpss.c - Driver for UART on Intel Braswell and various other Intel SoCs
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*
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* Copyright (C) 2016 Intel Corporation
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* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/bitops.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/rational.h>
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#include <linux/dmaengine.h>
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#include <linux/platform_data/dma-dw.h>
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#include "8250.h"
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#define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a
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#define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c
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#define PCI_DEVICE_ID_INTEL_BSW_UART1 0x228a
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#define PCI_DEVICE_ID_INTEL_BSW_UART2 0x228c
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#define PCI_DEVICE_ID_INTEL_BDW_UART1 0x9ce3
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#define PCI_DEVICE_ID_INTEL_BDW_UART2 0x9ce4
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/* Intel LPSS specific registers */
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#define BYT_PRV_CLK 0x800
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#define BYT_PRV_CLK_EN BIT(0)
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#define BYT_PRV_CLK_M_VAL_SHIFT 1
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#define BYT_PRV_CLK_N_VAL_SHIFT 16
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#define BYT_PRV_CLK_UPDATE BIT(31)
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#define BYT_TX_OVF_INT 0x820
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#define BYT_TX_OVF_INT_MASK BIT(1)
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struct lpss8250;
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struct lpss8250_board {
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unsigned long freq;
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unsigned int base_baud;
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int (*setup)(struct lpss8250 *, struct uart_port *p);
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};
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struct lpss8250 {
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int line;
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struct lpss8250_board *board;
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/* DMA parameters */
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struct uart_8250_dma dma;
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struct dw_dma_slave dma_param;
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u8 dma_maxburst;
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};
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static void byt_set_termios(struct uart_port *p, struct ktermios *termios,
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struct ktermios *old)
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{
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unsigned int baud = tty_termios_baud_rate(termios);
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struct lpss8250 *lpss = p->private_data;
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unsigned long fref = lpss->board->freq, fuart = baud * 16;
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unsigned long w = BIT(15) - 1;
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unsigned long m, n;
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u32 reg;
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/* Gracefully handle the B0 case: fall back to B9600 */
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fuart = fuart ? fuart : 9600 * 16;
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/* Get Fuart closer to Fref */
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fuart *= rounddown_pow_of_two(fref / fuart);
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/*
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* For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
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* dividers must be adjusted.
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*
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* uartclk = (m / n) * 100 MHz, where m <= n
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*/
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rational_best_approximation(fuart, fref, w, w, &m, &n);
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p->uartclk = fuart;
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/* Reset the clock */
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reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
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writel(reg, p->membase + BYT_PRV_CLK);
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reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
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writel(reg, p->membase + BYT_PRV_CLK);
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p->status &= ~UPSTAT_AUTOCTS;
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if (termios->c_cflag & CRTSCTS)
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p->status |= UPSTAT_AUTOCTS;
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serial8250_do_set_termios(p, termios, old);
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}
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static unsigned int byt_get_mctrl(struct uart_port *port)
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{
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unsigned int ret = serial8250_do_get_mctrl(port);
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/* Force DCD and DSR signals to permanently be reported as active */
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ret |= TIOCM_CAR | TIOCM_DSR;
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return ret;
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}
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static int byt_serial_setup(struct lpss8250 *lpss, struct uart_port *port)
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{
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struct dw_dma_slave *param = &lpss->dma_param;
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struct uart_8250_port *up = up_to_u8250p(port);
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struct pci_dev *pdev = to_pci_dev(port->dev);
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unsigned int dma_devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), 0);
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struct pci_dev *dma_dev = pci_get_slot(pdev->bus, dma_devfn);
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switch (pdev->device) {
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case PCI_DEVICE_ID_INTEL_BYT_UART1:
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case PCI_DEVICE_ID_INTEL_BSW_UART1:
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case PCI_DEVICE_ID_INTEL_BDW_UART1:
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param->src_id = 3;
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param->dst_id = 2;
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break;
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case PCI_DEVICE_ID_INTEL_BYT_UART2:
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case PCI_DEVICE_ID_INTEL_BSW_UART2:
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case PCI_DEVICE_ID_INTEL_BDW_UART2:
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param->src_id = 5;
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param->dst_id = 4;
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break;
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default:
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return -EINVAL;
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}
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param->dma_dev = &dma_dev->dev;
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param->m_master = 0;
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param->p_master = 1;
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/* TODO: Detect FIFO size automaticaly for DesignWare 8250 */
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port->fifosize = 64;
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up->tx_loadsz = 64;
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lpss->dma_maxburst = 16;
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port->set_termios = byt_set_termios;
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port->get_mctrl = byt_get_mctrl;
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/* Disable TX counter interrupts */
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writel(BYT_TX_OVF_INT_MASK, port->membase + BYT_TX_OVF_INT);
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return 0;
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}
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static bool lpss8250_dma_filter(struct dma_chan *chan, void *param)
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{
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struct dw_dma_slave *dws = param;
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if (dws->dma_dev != chan->device->dev)
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return false;
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chan->private = dws;
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return true;
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}
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static int lpss8250_dma_setup(struct lpss8250 *lpss, struct uart_8250_port *port)
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{
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struct uart_8250_dma *dma = &lpss->dma;
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struct dw_dma_slave *rx_param, *tx_param;
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struct device *dev = port->port.dev;
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rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
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if (!rx_param)
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return -ENOMEM;
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tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
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if (!tx_param)
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return -ENOMEM;
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*rx_param = lpss->dma_param;
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dma->rxconf.src_maxburst = lpss->dma_maxburst;
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*tx_param = lpss->dma_param;
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dma->txconf.dst_maxburst = lpss->dma_maxburst;
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dma->fn = lpss8250_dma_filter;
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dma->rx_param = rx_param;
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dma->tx_param = tx_param;
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port->dma = dma;
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return 0;
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}
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static int lpss8250_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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{
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struct uart_8250_port uart;
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struct lpss8250 *lpss;
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int ret;
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ret = pcim_enable_device(pdev);
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if (ret)
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return ret;
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pci_set_master(pdev);
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lpss = devm_kzalloc(&pdev->dev, sizeof(*lpss), GFP_KERNEL);
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if (!lpss)
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return -ENOMEM;
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lpss->board = (struct lpss8250_board *)id->driver_data;
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memset(&uart, 0, sizeof(struct uart_8250_port));
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uart.port.dev = &pdev->dev;
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uart.port.irq = pdev->irq;
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uart.port.private_data = lpss;
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uart.port.type = PORT_16550A;
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uart.port.iotype = UPIO_MEM;
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uart.port.regshift = 2;
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uart.port.uartclk = lpss->board->base_baud * 16;
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uart.port.flags = UPF_SHARE_IRQ | UPF_FIXED_PORT | UPF_FIXED_TYPE;
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uart.capabilities = UART_CAP_FIFO | UART_CAP_AFE;
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uart.port.mapbase = pci_resource_start(pdev, 0);
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uart.port.membase = pcim_iomap(pdev, 0, 0);
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if (!uart.port.membase)
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return -ENOMEM;
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ret = lpss->board->setup(lpss, &uart.port);
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if (ret)
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return ret;
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ret = lpss8250_dma_setup(lpss, &uart);
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if (ret)
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return ret;
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ret = serial8250_register_8250_port(&uart);
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if (ret < 0)
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return ret;
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lpss->line = ret;
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pci_set_drvdata(pdev, lpss);
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return 0;
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}
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static void lpss8250_remove(struct pci_dev *pdev)
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{
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struct lpss8250 *lpss = pci_get_drvdata(pdev);
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serial8250_unregister_port(lpss->line);
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}
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static const struct lpss8250_board byt_board = {
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.freq = 100000000,
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.base_baud = 2764800,
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.setup = byt_serial_setup,
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};
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#define LPSS_DEVICE(id, board) { PCI_VDEVICE(INTEL, id), (kernel_ulong_t)&board }
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static const struct pci_device_id pci_ids[] = {
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LPSS_DEVICE(PCI_DEVICE_ID_INTEL_BYT_UART1, byt_board),
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LPSS_DEVICE(PCI_DEVICE_ID_INTEL_BYT_UART2, byt_board),
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LPSS_DEVICE(PCI_DEVICE_ID_INTEL_BSW_UART1, byt_board),
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LPSS_DEVICE(PCI_DEVICE_ID_INTEL_BSW_UART2, byt_board),
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LPSS_DEVICE(PCI_DEVICE_ID_INTEL_BDW_UART1, byt_board),
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LPSS_DEVICE(PCI_DEVICE_ID_INTEL_BDW_UART2, byt_board),
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{ },
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};
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MODULE_DEVICE_TABLE(pci, pci_ids);
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static struct pci_driver lpss8250_pci_driver = {
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.name = "8250_lpss",
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.id_table = pci_ids,
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.probe = lpss8250_probe,
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.remove = lpss8250_remove,
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};
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module_pci_driver(lpss8250_pci_driver);
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MODULE_AUTHOR("Intel Corporation");
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("Intel LPSS UART driver");
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@ -21,14 +21,10 @@
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#include <linux/serial_core.h>
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#include <linux/8250_pci.h>
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#include <linux/bitops.h>
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#include <linux/rational.h>
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#include <asm/byteorder.h>
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#include <asm/io.h>
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#include <linux/dmaengine.h>
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#include <linux/platform_data/dma-dw.h>
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#include "8250.h"
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/*
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@ -1349,160 +1345,6 @@ ce4100_serial_setup(struct serial_private *priv,
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return ret;
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}
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#define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a
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#define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c
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#define PCI_DEVICE_ID_INTEL_BSW_UART1 0x228a
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#define PCI_DEVICE_ID_INTEL_BSW_UART2 0x228c
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#define PCI_DEVICE_ID_INTEL_BDW_UART1 0x9ce3
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#define PCI_DEVICE_ID_INTEL_BDW_UART2 0x9ce4
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#define BYT_PRV_CLK 0x800
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#define BYT_PRV_CLK_EN (1 << 0)
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#define BYT_PRV_CLK_M_VAL_SHIFT 1
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#define BYT_PRV_CLK_N_VAL_SHIFT 16
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#define BYT_PRV_CLK_UPDATE (1 << 31)
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#define BYT_TX_OVF_INT 0x820
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#define BYT_TX_OVF_INT_MASK (1 << 1)
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static void
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byt_set_termios(struct uart_port *p, struct ktermios *termios,
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struct ktermios *old)
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{
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unsigned int baud = tty_termios_baud_rate(termios);
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unsigned long fref = 100000000, fuart = baud * 16;
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unsigned long w = BIT(15) - 1;
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unsigned long m, n;
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u32 reg;
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/* Gracefully handle the B0 case: fall back to B9600 */
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fuart = fuart ? fuart : 9600 * 16;
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/* Get Fuart closer to Fref */
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fuart *= rounddown_pow_of_two(fref / fuart);
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/*
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* For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
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* dividers must be adjusted.
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*
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* uartclk = (m / n) * 100 MHz, where m <= n
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*/
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rational_best_approximation(fuart, fref, w, w, &m, &n);
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p->uartclk = fuart;
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/* Reset the clock */
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reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
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writel(reg, p->membase + BYT_PRV_CLK);
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reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
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writel(reg, p->membase + BYT_PRV_CLK);
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p->status &= ~UPSTAT_AUTOCTS;
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if (termios->c_cflag & CRTSCTS)
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p->status |= UPSTAT_AUTOCTS;
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serial8250_do_set_termios(p, termios, old);
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}
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static bool byt_dma_filter(struct dma_chan *chan, void *param)
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{
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struct dw_dma_slave *dws = param;
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if (dws->dma_dev != chan->device->dev)
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return false;
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chan->private = dws;
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return true;
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}
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static unsigned int
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byt_get_mctrl(struct uart_port *port)
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{
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unsigned int ret = serial8250_do_get_mctrl(port);
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/* Force DCD and DSR signals to permanently be reported as active. */
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ret |= TIOCM_CAR | TIOCM_DSR;
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return ret;
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}
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static int
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byt_serial_setup(struct serial_private *priv,
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const struct pciserial_board *board,
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struct uart_8250_port *port, int idx)
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{
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struct pci_dev *pdev = priv->dev;
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struct device *dev = port->port.dev;
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struct uart_8250_dma *dma;
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struct dw_dma_slave *tx_param, *rx_param;
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struct pci_dev *dma_dev;
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int ret;
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dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
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if (!dma)
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return -ENOMEM;
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tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
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if (!tx_param)
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return -ENOMEM;
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rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
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if (!rx_param)
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return -ENOMEM;
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switch (pdev->device) {
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case PCI_DEVICE_ID_INTEL_BYT_UART1:
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case PCI_DEVICE_ID_INTEL_BSW_UART1:
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case PCI_DEVICE_ID_INTEL_BDW_UART1:
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rx_param->src_id = 3;
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tx_param->dst_id = 2;
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break;
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case PCI_DEVICE_ID_INTEL_BYT_UART2:
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case PCI_DEVICE_ID_INTEL_BSW_UART2:
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case PCI_DEVICE_ID_INTEL_BDW_UART2:
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rx_param->src_id = 5;
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tx_param->dst_id = 4;
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break;
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default:
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return -EINVAL;
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}
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rx_param->m_master = 0;
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rx_param->p_master = 1;
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dma->rxconf.src_maxburst = 16;
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tx_param->m_master = 0;
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tx_param->p_master = 1;
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dma->txconf.dst_maxburst = 16;
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dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
|
||||
rx_param->dma_dev = &dma_dev->dev;
|
||||
tx_param->dma_dev = &dma_dev->dev;
|
||||
|
||||
dma->fn = byt_dma_filter;
|
||||
dma->rx_param = rx_param;
|
||||
dma->tx_param = tx_param;
|
||||
|
||||
ret = pci_default_setup(priv, board, port, idx);
|
||||
port->port.iotype = UPIO_MEM;
|
||||
port->port.type = PORT_16550A;
|
||||
port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
|
||||
port->port.set_termios = byt_set_termios;
|
||||
port->port.get_mctrl = byt_get_mctrl;
|
||||
port->port.fifosize = 64;
|
||||
port->tx_loadsz = 64;
|
||||
port->dma = dma;
|
||||
port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
|
||||
|
||||
/* Disable Tx counter interrupts */
|
||||
writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int
|
||||
pci_omegapci_setup(struct serial_private *priv,
|
||||
const struct pciserial_board *board,
|
||||
@ -2041,48 +1883,6 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
|
||||
.subdevice = PCI_ANY_ID,
|
||||
.setup = kt_serial_setup,
|
||||
},
|
||||
{
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = PCI_DEVICE_ID_INTEL_BYT_UART1,
|
||||
.subvendor = PCI_ANY_ID,
|
||||
.subdevice = PCI_ANY_ID,
|
||||
.setup = byt_serial_setup,
|
||||
},
|
||||
{
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = PCI_DEVICE_ID_INTEL_BYT_UART2,
|
||||
.subvendor = PCI_ANY_ID,
|
||||
.subdevice = PCI_ANY_ID,
|
||||
.setup = byt_serial_setup,
|
||||
},
|
||||
{
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = PCI_DEVICE_ID_INTEL_BSW_UART1,
|
||||
.subvendor = PCI_ANY_ID,
|
||||
.subdevice = PCI_ANY_ID,
|
||||
.setup = byt_serial_setup,
|
||||
},
|
||||
{
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = PCI_DEVICE_ID_INTEL_BSW_UART2,
|
||||
.subvendor = PCI_ANY_ID,
|
||||
.subdevice = PCI_ANY_ID,
|
||||
.setup = byt_serial_setup,
|
||||
},
|
||||
{
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = PCI_DEVICE_ID_INTEL_BDW_UART1,
|
||||
.subvendor = PCI_ANY_ID,
|
||||
.subdevice = PCI_ANY_ID,
|
||||
.setup = byt_serial_setup,
|
||||
},
|
||||
{
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = PCI_DEVICE_ID_INTEL_BDW_UART2,
|
||||
.subvendor = PCI_ANY_ID,
|
||||
.subdevice = PCI_ANY_ID,
|
||||
.setup = byt_serial_setup,
|
||||
},
|
||||
/*
|
||||
* ITE
|
||||
*/
|
||||
@ -2955,7 +2755,6 @@ enum pci_board_num_t {
|
||||
pbn_ADDIDATA_PCIe_4_3906250,
|
||||
pbn_ADDIDATA_PCIe_8_3906250,
|
||||
pbn_ce4100_1_115200,
|
||||
pbn_byt,
|
||||
pbn_qrk,
|
||||
pbn_omegapci,
|
||||
pbn_NETMOS9900_2s_115200,
|
||||
@ -3732,12 +3531,6 @@ static struct pciserial_board pci_boards[] = {
|
||||
.base_baud = 921600,
|
||||
.reg_shift = 2,
|
||||
},
|
||||
[pbn_byt] = {
|
||||
.flags = FL_BASE0,
|
||||
.num_ports = 1,
|
||||
.base_baud = 2764800,
|
||||
.reg_shift = 2,
|
||||
},
|
||||
[pbn_qrk] = {
|
||||
.flags = FL_BASE0,
|
||||
.num_ports = 1,
|
||||
@ -3855,6 +3648,14 @@ static const struct pci_device_id blacklist[] = {
|
||||
{ PCI_VDEVICE(INTEL, 0x081d), },
|
||||
{ PCI_VDEVICE(INTEL, 0x1191), },
|
||||
{ PCI_VDEVICE(INTEL, 0x19d8), },
|
||||
|
||||
/* Intel platforms with DesignWare UART */
|
||||
{ PCI_VDEVICE(INTEL, 0x0f0a), },
|
||||
{ PCI_VDEVICE(INTEL, 0x0f0c), },
|
||||
{ PCI_VDEVICE(INTEL, 0x228a), },
|
||||
{ PCI_VDEVICE(INTEL, 0x228c), },
|
||||
{ PCI_VDEVICE(INTEL, 0x9ce3), },
|
||||
{ PCI_VDEVICE(INTEL, 0x9ce4), },
|
||||
};
|
||||
|
||||
/*
|
||||
@ -5520,33 +5321,6 @@ static struct pci_device_id serial_pci_tbl[] = {
|
||||
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
|
||||
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
|
||||
pbn_ce4100_1_115200 },
|
||||
/* Intel BayTrail */
|
||||
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
|
||||
PCI_ANY_ID, PCI_ANY_ID,
|
||||
PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
|
||||
pbn_byt },
|
||||
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
|
||||
PCI_ANY_ID, PCI_ANY_ID,
|
||||
PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
|
||||
pbn_byt },
|
||||
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1,
|
||||
PCI_ANY_ID, PCI_ANY_ID,
|
||||
PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
|
||||
pbn_byt },
|
||||
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2,
|
||||
PCI_ANY_ID, PCI_ANY_ID,
|
||||
PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
|
||||
pbn_byt },
|
||||
|
||||
/* Intel Broadwell */
|
||||
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART1,
|
||||
PCI_ANY_ID, PCI_ANY_ID,
|
||||
PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
|
||||
pbn_byt },
|
||||
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BDW_UART2,
|
||||
PCI_ANY_ID, PCI_ANY_ID,
|
||||
PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
|
||||
pbn_byt },
|
||||
|
||||
/*
|
||||
* Intel Quark x1000
|
||||
|
||||
@ -121,7 +121,6 @@ config SERIAL_8250_PCI
|
||||
tristate "8250/16550 PCI device support" if EXPERT
|
||||
depends on SERIAL_8250 && PCI
|
||||
default SERIAL_8250
|
||||
select RATIONAL
|
||||
help
|
||||
This builds standard PCI serial support. You may be able to
|
||||
disable this feature if you only need legacy serial support.
|
||||
@ -403,6 +402,20 @@ config SERIAL_8250_INGENIC
|
||||
If you have a system using an Ingenic SoC and wish to make use of
|
||||
its UARTs, say Y to this option. If unsure, say N.
|
||||
|
||||
config SERIAL_8250_LPSS
|
||||
tristate "Support for serial ports on Intel LPSS platforms" if EXPERT
|
||||
default SERIAL_8250
|
||||
depends on SERIAL_8250 && PCI
|
||||
depends on X86 || COMPILE_TEST
|
||||
select DW_DMAC_CORE if SERIAL_8250_DMA
|
||||
select DW_DMAC_PCI if (SERIAL_8250_DMA && X86_INTEL_LPSS)
|
||||
select RATIONAL
|
||||
help
|
||||
Selecting this option will enable handling of the extra features
|
||||
present on the UART found on various Intel platforms such as:
|
||||
- Intel Baytrail SoC
|
||||
- Intel Braswell SoC
|
||||
|
||||
config SERIAL_8250_MID
|
||||
tristate "Support for serial ports on Intel MID platforms" if EXPERT
|
||||
default SERIAL_8250
|
||||
|
||||
@ -28,6 +28,7 @@ obj-$(CONFIG_SERIAL_8250_LPC18XX) += 8250_lpc18xx.o
|
||||
obj-$(CONFIG_SERIAL_8250_MT6577) += 8250_mtk.o
|
||||
obj-$(CONFIG_SERIAL_8250_UNIPHIER) += 8250_uniphier.o
|
||||
obj-$(CONFIG_SERIAL_8250_INGENIC) += 8250_ingenic.o
|
||||
obj-$(CONFIG_SERIAL_8250_LPSS) += 8250_lpss.o
|
||||
obj-$(CONFIG_SERIAL_8250_MID) += 8250_mid.o
|
||||
obj-$(CONFIG_SERIAL_8250_MOXA) += 8250_moxa.o
|
||||
obj-$(CONFIG_SERIAL_OF_PLATFORM) += 8250_of.o
|
||||
|
||||
Loading…
Reference in New Issue
Block a user