mirror of
https://github.com/torvalds/linux.git
synced 2024-11-08 21:21:47 +00:00
drm/nouveau/pbus: add a PBUS subdev that hands IRQs to the right subdevs
We are going to use PTHERM's IRQs for thermal monitoring but we need to route them first. On nv31-50, PBUS's IRQ line is shared with GPIOs IRQs. It seems like nv10-31 GPIO interruptions aren't well handled. I kept the original behaviour but it is wrong and may lead to an IRQ storm. Since we enable all PBUS IRQs, we need a way to avoid being stormed if we don't handle them. The solution I used was to mask the IRQs that have not been handled. This will also print one message in the logs to let us know. v2: drop the shared intr handler because of was racy v3: style fixes v4: drop a useless construct in the chipset-dependent INTR v5: add BUS to the disable mask v6 (Ben Skeggs): - general tidy to match the rest of the driver's style - nva3->nvc0, nva3 can be serviced just fine with nv50.c, rnndb even notes that the THERM_ALARM bit got left in the hw until fermi anyway.. so, it's not going to conflict - removed the peephole and user stuff, for the moment.. will handle them later if we find a good reason to actually care.. - limited INTR_EN to just what we can handle for now, mostly to prevent spam of unknown status bits (seen on at least nv4x) Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Martin Peres <martin.peres@labri.fr>
This commit is contained in:
Martin Peres
Ben Skeggs
parent
694472f417
commit
a10220bbf8
@ -40,6 +40,10 @@ nouveau-y += core/subdev/bios/mxm.o
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nouveau-y += core/subdev/bios/perf.o
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nouveau-y += core/subdev/bios/pll.o
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nouveau-y += core/subdev/bios/therm.o
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nouveau-y += core/subdev/bus/nv04.o
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nouveau-y += core/subdev/bus/nv31.o
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nouveau-y += core/subdev/bus/nv50.o
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nouveau-y += core/subdev/bus/nvc0.o
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nouveau-y += core/subdev/clock/nv04.o
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nouveau-y += core/subdev/clock/nv40.o
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nouveau-y += core/subdev/clock/nv50.o
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@ -26,6 +26,7 @@ enum nv_subdev_type {
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*/
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NVDEV_SUBDEV_MXM,
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NVDEV_SUBDEV_MC,
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NVDEV_SUBDEV_BUS,
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NVDEV_SUBDEV_TIMER,
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NVDEV_SUBDEV_FB,
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NVDEV_SUBDEV_LTCG,
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41
drivers/gpu/drm/nouveau/core/include/subdev/bus.h
Normal file
41
drivers/gpu/drm/nouveau/core/include/subdev/bus.h
Normal file
@ -0,0 +1,41 @@
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#ifndef __NOUVEAU_BUS_H__
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#define __NOUVEAU_BUS_H__
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#include <core/subdev.h>
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#include <core/device.h>
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struct nouveau_bus_intr {
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u32 stat;
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u32 unit;
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};
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struct nouveau_bus {
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struct nouveau_subdev base;
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};
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static inline struct nouveau_bus *
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nouveau_bus(void *obj)
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{
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return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_BUS];
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}
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#define nouveau_bus_create(p, e, o, d) \
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nouveau_subdev_create_((p), (e), (o), 0, "PBUS", "master", \
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sizeof(**d), (void **)d)
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#define nouveau_bus_destroy(p) \
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nouveau_subdev_destroy(&(p)->base)
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#define nouveau_bus_init(p) \
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nouveau_subdev_init(&(p)->base)
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#define nouveau_bus_fini(p, s) \
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nouveau_subdev_fini(&(p)->base, (s))
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#define _nouveau_bus_dtor _nouveau_subdev_dtor
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#define _nouveau_bus_init _nouveau_subdev_init
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#define _nouveau_bus_fini _nouveau_subdev_fini
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extern struct nouveau_oclass nv04_bus_oclass;
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extern struct nouveau_oclass nv31_bus_oclass;
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extern struct nouveau_oclass nv50_bus_oclass;
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extern struct nouveau_oclass nvc0_bus_oclass;
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#endif
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95
drivers/gpu/drm/nouveau/core/subdev/bus/nv04.c
Normal file
95
drivers/gpu/drm/nouveau/core/subdev/bus/nv04.c
Normal file
@ -0,0 +1,95 @@
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/*
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* Copyright 2012 Nouveau Community
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Martin Peres <martin.peres@labri.fr>
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* Ben Skeggs
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*/
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#include <subdev/bus.h>
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struct nv04_bus_priv {
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struct nouveau_bus base;
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};
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void
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nv04_bus_intr(struct nouveau_subdev *subdev)
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{
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struct nouveau_bus *pbus = nouveau_bus(subdev);
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u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);
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if (stat & 0x00000001) {
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nv_error(pbus, "BUS ERROR\n");
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stat &= ~0x00000001;
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nv_wr32(pbus, 0x001100, 0x00000001);
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}
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if (stat & 0x00000110) {
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subdev = nouveau_subdev(subdev, NVDEV_SUBDEV_GPIO);
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if (subdev && subdev->intr)
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subdev->intr(subdev);
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stat &= ~0x00000110;
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nv_wr32(pbus, 0x001100, 0x00000110);
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}
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if (stat) {
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nv_error(pbus, "unknown intr 0x%08x\n", stat);
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nv_mask(pbus, 0x001140, stat, 0x00000000);
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}
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}
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static int
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nv04_bus_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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struct nouveau_oclass *oclass, void *data, u32 size,
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struct nouveau_object **pobject)
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{
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struct nv04_bus_priv *priv;
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int ret;
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ret = nouveau_bus_create(parent, engine, oclass, &priv);
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*pobject = nv_object(priv);
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if (ret)
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return ret;
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nv_subdev(priv)->intr = nv04_bus_intr;
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return 0;
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}
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static int
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nv04_bus_init(struct nouveau_object *object)
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{
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struct nv04_bus_priv *priv = (void *)object;
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nv_wr32(priv, 0x001100, 0xffffffff);
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nv_wr32(priv, 0x001140, 0x00000111);
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return nouveau_bus_init(&priv->base);
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}
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struct nouveau_oclass
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nv04_bus_oclass = {
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.handle = NV_SUBDEV(BUS, 0x04),
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.ofuncs = &(struct nouveau_ofuncs) {
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.ctor = nv04_bus_ctor,
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.dtor = _nouveau_bus_dtor,
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.init = nv04_bus_init,
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.fini = _nouveau_bus_fini,
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},
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};
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106
drivers/gpu/drm/nouveau/core/subdev/bus/nv31.c
Normal file
106
drivers/gpu/drm/nouveau/core/subdev/bus/nv31.c
Normal file
@ -0,0 +1,106 @@
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/*
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* Copyright 2012 Nouveau Community
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Martin Peres <martin.peres@labri.fr>
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* Ben Skeggs
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*/
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#include <subdev/bus.h>
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struct nv31_bus_priv {
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struct nouveau_bus base;
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};
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static void
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nv31_bus_intr(struct nouveau_subdev *subdev)
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{
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struct nouveau_bus *pbus = nouveau_bus(subdev);
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u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);
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u32 gpio = nv_rd32(pbus, 0x001104) & nv_rd32(pbus, 0x001144);
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if (gpio) {
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subdev = nouveau_subdev(pbus, NVDEV_SUBDEV_GPIO);
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if (subdev && subdev->intr)
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subdev->intr(subdev);
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}
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if (stat & 0x00000008) {
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nv_error(pbus, "MMIO FAULT\n"); /* NV41- */
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stat &= ~0x00000008;
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nv_wr32(pbus, 0x001100, 0x00000008);
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}
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if (stat & 0x00070000) {
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subdev = nouveau_subdev(pbus, NVDEV_SUBDEV_THERM);
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if (subdev && subdev->intr)
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subdev->intr(subdev);
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stat &= ~0x00070000;
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nv_wr32(pbus, 0x001100, 0x00070000);
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}
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if (stat) {
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nv_error(pbus, "unknown intr 0x%08x\n", stat);
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nv_mask(pbus, 0x001140, stat, 0x00000000);
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}
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}
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static int
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nv31_bus_init(struct nouveau_object *object)
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{
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struct nv31_bus_priv *priv = (void *)object;
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int ret;
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ret = nouveau_bus_init(&priv->base);
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if (ret)
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return ret;
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nv_wr32(priv, 0x001100, 0xffffffff);
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nv_wr32(priv, 0x001140, 0x00070008);
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return 0;
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}
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static int
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nv31_bus_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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struct nouveau_oclass *oclass, void *data, u32 size,
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struct nouveau_object **pobject)
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{
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struct nv31_bus_priv *priv;
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int ret;
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ret = nouveau_bus_create(parent, engine, oclass, &priv);
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*pobject = nv_object(priv);
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if (ret)
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return ret;
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nv_subdev(priv)->intr = nv31_bus_intr;
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return 0;
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}
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struct nouveau_oclass
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nv31_bus_oclass = {
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.handle = NV_SUBDEV(BUS, 0x31),
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.ofuncs = &(struct nouveau_ofuncs) {
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.ctor = nv31_bus_ctor,
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.dtor = _nouveau_bus_dtor,
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.init = nv31_bus_init,
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.fini = _nouveau_bus_fini,
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},
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};
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99
drivers/gpu/drm/nouveau/core/subdev/bus/nv50.c
Normal file
99
drivers/gpu/drm/nouveau/core/subdev/bus/nv50.c
Normal file
@ -0,0 +1,99 @@
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/*
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* Copyright 2012 Nouveau Community
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
|
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* to deal in the Software without restriction, including without limitation
|
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
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*
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||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
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||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Martin Peres <martin.peres@labri.fr>
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* Ben Skeggs
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*/
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#include <subdev/bus.h>
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struct nv50_bus_priv {
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struct nouveau_bus base;
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};
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static void
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nv50_bus_intr(struct nouveau_subdev *subdev)
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{
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struct nouveau_bus *pbus = nouveau_bus(subdev);
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u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);
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if (stat & 0x00000008) {
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nv_error(pbus, "MMIO FAULT\n");
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stat &= ~0x00000008;
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nv_wr32(pbus, 0x001100, 0x00000008);
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}
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if (stat & 0x00010000) {
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subdev = nouveau_subdev(pbus, NVDEV_SUBDEV_THERM);
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if (subdev && subdev->intr)
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subdev->intr(subdev);
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stat &= ~0x00010000;
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nv_wr32(pbus, 0x001100, 0x00010000);
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}
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if (stat) {
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nv_error(pbus, "unknown intr 0x%08x\n", stat);
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nv_mask(pbus, 0x001140, stat, 0);
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}
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}
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static int
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nv50_bus_init(struct nouveau_object *object)
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{
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struct nv50_bus_priv *priv = (void *)object;
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int ret;
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ret = nouveau_bus_init(&priv->base);
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if (ret)
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return ret;
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nv_wr32(priv, 0x001100, 0xffffffff);
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nv_wr32(priv, 0x001140, 0x00010008);
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return 0;
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}
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static int
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nv50_bus_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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struct nouveau_oclass *oclass, void *data, u32 size,
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struct nouveau_object **pobject)
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{
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struct nv50_bus_priv *priv;
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int ret;
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ret = nouveau_bus_create(parent, engine, oclass, &priv);
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*pobject = nv_object(priv);
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if (ret)
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return ret;
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nv_subdev(priv)->intr = nv50_bus_intr;
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return 0;
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}
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struct nouveau_oclass
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nv50_bus_oclass = {
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.handle = NV_SUBDEV(BUS, 0x50),
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.ofuncs = &(struct nouveau_ofuncs) {
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.ctor = nv50_bus_ctor,
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.dtor = _nouveau_bus_dtor,
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.init = nv50_bus_init,
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.fini = _nouveau_bus_fini,
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},
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};
|
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96
drivers/gpu/drm/nouveau/core/subdev/bus/nvc0.c
Normal file
96
drivers/gpu/drm/nouveau/core/subdev/bus/nvc0.c
Normal file
@ -0,0 +1,96 @@
|
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/*
|
||||
* Copyright 2012 Nouveau Community
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Martin Peres <martin.peres@labri.fr>
|
||||
* Ben Skeggs
|
||||
*/
|
||||
|
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#include <subdev/bus.h>
|
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|
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struct nvc0_bus_priv {
|
||||
struct nouveau_bus base;
|
||||
};
|
||||
|
||||
static void
|
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nvc0_bus_intr(struct nouveau_subdev *subdev)
|
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{
|
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struct nouveau_bus *pbus = nouveau_bus(subdev);
|
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u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);
|
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|
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if (stat & 0x0000000e) {
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nv_error(pbus, "MMIO FAULT [");
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if (stat & 0x00000002) pr_cont(" !ENGINE");
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if (stat & 0x00000004) pr_cont(" IBUS");
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if (stat & 0x00000004) pr_cont(" TIMEOUT");
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pr_cont("]\n");
|
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|
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nv_wr32(pbus, 0x001100, (stat & 0x0000000e));
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stat &= ~0x0000000e;
|
||||
}
|
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|
||||
if (stat) {
|
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nv_error(pbus, "unknown intr 0x%08x\n", stat);
|
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nv_mask(pbus, 0x001140, stat, 0x00000000);
|
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}
|
||||
}
|
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|
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static int
|
||||
nvc0_bus_init(struct nouveau_object *object)
|
||||
{
|
||||
struct nvc0_bus_priv *priv = (void *)object;
|
||||
int ret;
|
||||
|
||||
ret = nouveau_bus_init(&priv->base);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
nv_wr32(priv, 0x001100, 0xffffffff);
|
||||
nv_wr32(priv, 0x001140, 0x0000000e);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
nvc0_bus_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
|
||||
struct nouveau_oclass *oclass, void *data, u32 size,
|
||||
struct nouveau_object **pobject)
|
||||
{
|
||||
struct nvc0_bus_priv *priv;
|
||||
int ret;
|
||||
|
||||
ret = nouveau_bus_create(parent, engine, oclass, &priv);
|
||||
*pobject = nv_object(priv);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
nv_subdev(priv)->intr = nvc0_bus_intr;
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct nouveau_oclass
|
||||
nvc0_bus_oclass = {
|
||||
.handle = NV_SUBDEV(BUS, 0xc0),
|
||||
.ofuncs = &(struct nouveau_ofuncs) {
|
||||
.ctor = nvc0_bus_ctor,
|
||||
.dtor = _nouveau_bus_dtor,
|
||||
.init = nvc0_bus_init,
|
||||
.fini = _nouveau_bus_fini,
|
||||
},
|
||||
};
|
||||
@ -66,6 +66,7 @@ static const u64 disable_map[] = {
|
||||
[NVDEV_SUBDEV_CLOCK] = NV_DEVICE_DISABLE_CORE,
|
||||
[NVDEV_SUBDEV_MXM] = NV_DEVICE_DISABLE_CORE,
|
||||
[NVDEV_SUBDEV_MC] = NV_DEVICE_DISABLE_CORE,
|
||||
[NVDEV_SUBDEV_BUS] = NV_DEVICE_DISABLE_CORE,
|
||||
[NVDEV_SUBDEV_TIMER] = NV_DEVICE_DISABLE_CORE,
|
||||
[NVDEV_SUBDEV_FB] = NV_DEVICE_DISABLE_CORE,
|
||||
[NVDEV_SUBDEV_LTCG] = NV_DEVICE_DISABLE_CORE,
|
||||
|
||||
@ -24,6 +24,7 @@
|
||||
|
||||
#include <subdev/device.h>
|
||||
#include <subdev/bios.h>
|
||||
#include <subdev/bus.h>
|
||||
#include <subdev/i2c.h>
|
||||
#include <subdev/clock.h>
|
||||
#include <subdev/devinit.h>
|
||||
@ -50,6 +51,7 @@ nv04_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv04_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv04_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
|
||||
@ -67,6 +69,7 @@ nv04_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv05_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv04_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
|
||||
|
||||
@ -24,6 +24,7 @@
|
||||
|
||||
#include <subdev/device.h>
|
||||
#include <subdev/bios.h>
|
||||
#include <subdev/bus.h>
|
||||
#include <subdev/gpio.h>
|
||||
#include <subdev/i2c.h>
|
||||
#include <subdev/clock.h>
|
||||
@ -52,6 +53,7 @@ nv10_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv10_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
|
||||
@ -68,6 +70,7 @@ nv10_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv10_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
|
||||
@ -86,6 +89,7 @@ nv10_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv10_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
|
||||
@ -104,6 +108,7 @@ nv10_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv1a_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
|
||||
@ -122,6 +127,7 @@ nv10_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv10_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
|
||||
@ -140,6 +146,7 @@ nv10_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv10_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
|
||||
@ -158,6 +165,7 @@ nv10_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv1a_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
|
||||
@ -176,6 +184,7 @@ nv10_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv10_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
|
||||
|
||||
@ -24,6 +24,7 @@
|
||||
|
||||
#include <subdev/device.h>
|
||||
#include <subdev/bios.h>
|
||||
#include <subdev/bus.h>
|
||||
#include <subdev/gpio.h>
|
||||
#include <subdev/i2c.h>
|
||||
#include <subdev/clock.h>
|
||||
@ -53,6 +54,7 @@ nv20_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv20_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
|
||||
@ -71,6 +73,7 @@ nv20_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv25_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
|
||||
@ -89,6 +92,7 @@ nv20_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv25_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
|
||||
@ -107,6 +111,7 @@ nv20_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv25_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
|
||||
|
||||
@ -24,6 +24,7 @@
|
||||
|
||||
#include <subdev/device.h>
|
||||
#include <subdev/bios.h>
|
||||
#include <subdev/bus.h>
|
||||
#include <subdev/gpio.h>
|
||||
#include <subdev/i2c.h>
|
||||
#include <subdev/clock.h>
|
||||
@ -53,6 +54,7 @@ nv30_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv30_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
|
||||
@ -71,6 +73,7 @@ nv30_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv35_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
|
||||
@ -89,6 +92,7 @@ nv30_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv30_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
|
||||
@ -108,6 +112,7 @@ nv30_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv36_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
|
||||
@ -127,6 +132,7 @@ nv30_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv10_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
|
||||
|
||||
@ -24,6 +24,8 @@
|
||||
|
||||
#include <subdev/device.h>
|
||||
#include <subdev/bios.h>
|
||||
#include <subdev/bus.h>
|
||||
#include <subdev/vm.h>
|
||||
#include <subdev/gpio.h>
|
||||
#include <subdev/i2c.h>
|
||||
#include <subdev/clock.h>
|
||||
@ -55,6 +57,7 @@ nv40_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
|
||||
@ -75,6 +78,7 @@ nv40_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv41_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
|
||||
@ -95,6 +99,7 @@ nv40_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv41_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
|
||||
@ -115,6 +120,7 @@ nv40_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv41_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
|
||||
@ -135,6 +141,7 @@ nv40_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
|
||||
@ -155,6 +162,7 @@ nv40_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv47_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
|
||||
@ -175,6 +183,7 @@ nv40_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv49_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
|
||||
@ -195,6 +204,7 @@ nv40_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv49_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
|
||||
@ -215,6 +225,7 @@ nv40_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv44_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
|
||||
@ -235,6 +246,7 @@ nv40_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv46_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
|
||||
@ -255,6 +267,7 @@ nv40_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv44_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
|
||||
@ -275,6 +288,7 @@ nv40_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv46_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
|
||||
@ -295,6 +309,7 @@ nv40_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv4e_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
|
||||
@ -315,6 +330,7 @@ nv40_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv46_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
|
||||
@ -335,6 +351,7 @@ nv40_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv46_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
|
||||
@ -355,6 +372,7 @@ nv40_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv46_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
|
||||
|
||||
@ -24,6 +24,7 @@
|
||||
|
||||
#include <subdev/device.h>
|
||||
#include <subdev/bios.h>
|
||||
#include <subdev/bus.h>
|
||||
#include <subdev/gpio.h>
|
||||
#include <subdev/i2c.h>
|
||||
#include <subdev/clock.h>
|
||||
@ -63,6 +64,7 @@ nv50_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
|
||||
@ -85,6 +87,7 @@ nv50_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
|
||||
@ -110,6 +113,7 @@ nv50_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
|
||||
@ -135,6 +139,7 @@ nv50_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
|
||||
@ -160,6 +165,7 @@ nv50_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
|
||||
@ -185,6 +191,7 @@ nv50_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
|
||||
@ -210,6 +217,7 @@ nv50_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
|
||||
@ -235,6 +243,7 @@ nv50_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
|
||||
@ -260,6 +269,7 @@ nv50_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
|
||||
@ -285,6 +295,7 @@ nv50_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
|
||||
@ -310,6 +321,7 @@ nv50_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
|
||||
@ -336,6 +348,7 @@ nv50_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
|
||||
@ -361,6 +374,7 @@ nv50_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
|
||||
@ -386,6 +400,7 @@ nv50_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
|
||||
|
||||
@ -24,6 +24,7 @@
|
||||
|
||||
#include <subdev/device.h>
|
||||
#include <subdev/bios.h>
|
||||
#include <subdev/bus.h>
|
||||
#include <subdev/gpio.h>
|
||||
#include <subdev/i2c.h>
|
||||
#include <subdev/clock.h>
|
||||
@ -63,6 +64,7 @@ nvc0_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
|
||||
@ -91,6 +93,7 @@ nvc0_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
|
||||
@ -119,6 +122,7 @@ nvc0_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
|
||||
@ -147,6 +151,7 @@ nvc0_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
|
||||
@ -175,6 +180,7 @@ nvc0_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
|
||||
@ -203,6 +209,7 @@ nvc0_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
|
||||
@ -231,6 +238,7 @@ nvc0_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
|
||||
@ -259,6 +267,7 @@ nvc0_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
|
||||
|
||||
@ -24,6 +24,7 @@
|
||||
|
||||
#include <subdev/device.h>
|
||||
#include <subdev/bios.h>
|
||||
#include <subdev/bus.h>
|
||||
#include <subdev/gpio.h>
|
||||
#include <subdev/i2c.h>
|
||||
#include <subdev/clock.h>
|
||||
@ -63,6 +64,7 @@ nve0_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
|
||||
@ -91,6 +93,7 @@ nve0_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
|
||||
@ -119,6 +122,7 @@ nve0_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
|
||||
|
||||
@ -141,8 +141,6 @@ nv10_gpio_init(struct nouveau_object *object)
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
nv_wr32(priv, 0x001140, 0x00000000);
|
||||
nv_wr32(priv, 0x001100, 0xffffffff);
|
||||
nv_wr32(priv, 0x001144, 0x00000000);
|
||||
nv_wr32(priv, 0x001104, 0xffffffff);
|
||||
return 0;
|
||||
@ -152,7 +150,6 @@ static int
|
||||
nv10_gpio_fini(struct nouveau_object *object, bool suspend)
|
||||
{
|
||||
struct nv10_gpio_priv *priv = (void *)object;
|
||||
nv_wr32(priv, 0x001140, 0x00000000);
|
||||
nv_wr32(priv, 0x001144, 0x00000000);
|
||||
return nouveau_gpio_fini(&priv->base, suspend);
|
||||
}
|
||||
|
||||
@ -37,7 +37,7 @@ nv04_mc_intr[] = {
|
||||
{ 0x00100000, NVDEV_SUBDEV_TIMER },
|
||||
{ 0x01000000, NVDEV_ENGINE_DISP }, /* NV04- PCRTC0 */
|
||||
{ 0x02000000, NVDEV_ENGINE_DISP }, /* NV11- PCRTC1 */
|
||||
{ 0x10000000, NVDEV_SUBDEV_GPIO }, /* PBUS */
|
||||
{ 0x10000000, NVDEV_SUBDEV_BUS },
|
||||
{ 0x80000000, NVDEV_ENGINE_SW },
|
||||
{}
|
||||
};
|
||||
|
||||
@ -38,6 +38,7 @@ nv50_mc_intr[] = {
|
||||
{ 0x00100000, NVDEV_SUBDEV_TIMER },
|
||||
{ 0x00200000, NVDEV_SUBDEV_GPIO },
|
||||
{ 0x04000000, NVDEV_ENGINE_DISP },
|
||||
{ 0x10000000, NVDEV_SUBDEV_BUS },
|
||||
{ 0x80000000, NVDEV_ENGINE_SW },
|
||||
{ 0x0000d101, NVDEV_SUBDEV_FB },
|
||||
{},
|
||||
|
||||
@ -39,6 +39,7 @@ nv98_mc_intr[] = {
|
||||
{ 0x00200000, NVDEV_SUBDEV_GPIO },
|
||||
{ 0x00400000, NVDEV_ENGINE_COPY0 }, /* NVA3- */
|
||||
{ 0x04000000, NVDEV_ENGINE_DISP },
|
||||
{ 0x10000000, NVDEV_SUBDEV_BUS },
|
||||
{ 0x80000000, NVDEV_ENGINE_SW },
|
||||
{ 0x0040d101, NVDEV_SUBDEV_FB },
|
||||
{},
|
||||
|
||||
@ -36,11 +36,13 @@ nvc0_mc_intr[] = {
|
||||
{ 0x00000100, NVDEV_ENGINE_FIFO },
|
||||
{ 0x00001000, NVDEV_ENGINE_GR },
|
||||
{ 0x00008000, NVDEV_ENGINE_BSP },
|
||||
{ 0x00040000, NVDEV_SUBDEV_THERM },
|
||||
{ 0x00020000, NVDEV_ENGINE_VP },
|
||||
{ 0x00100000, NVDEV_SUBDEV_TIMER },
|
||||
{ 0x00200000, NVDEV_SUBDEV_GPIO },
|
||||
{ 0x02000000, NVDEV_SUBDEV_LTCG },
|
||||
{ 0x04000000, NVDEV_ENGINE_DISP },
|
||||
{ 0x10000000, NVDEV_SUBDEV_BUS },
|
||||
{ 0x40000000, NVDEV_SUBDEV_IBUS },
|
||||
{ 0x80000000, NVDEV_ENGINE_SW },
|
||||
{},
|
||||
|
||||
Loading…
Reference in New Issue
Block a user