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https://github.com/torvalds/linux.git
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drm/nv20-nv30/gr: move to exec engine interface
A bit of cleanup done along the way, but, like nv40/nv50, needs more. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
39c8d36827
commit
a0b1de84fe
@ -1167,13 +1167,7 @@ extern struct nouveau_bitfield nv10_graph_intr[];
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extern struct nouveau_bitfield nv10_graph_nstatus[];
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/* nv20_graph.c */
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extern int nv20_graph_create_context(struct nouveau_channel *);
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extern void nv20_graph_destroy_context(struct nouveau_channel *);
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extern int nv20_graph_load_context(struct nouveau_channel *);
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extern int nv20_graph_unload_context(struct drm_device *);
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extern int nv20_graph_init(struct drm_device *);
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extern void nv20_graph_takedown(struct drm_device *);
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extern int nv30_graph_init(struct drm_device *);
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extern int nv20_graph_create(struct drm_device *);
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extern void nv20_graph_set_tile_region(struct drm_device *dev, int i);
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/* nv40_graph.c */
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@ -180,15 +180,10 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
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engine->fb.init_tile_region = nv10_fb_init_tile_region;
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engine->fb.set_tile_region = nv10_fb_set_tile_region;
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engine->fb.free_tile_region = nv10_fb_free_tile_region;
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engine->graph.init = nv20_graph_init;
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engine->graph.takedown = nv20_graph_takedown;
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engine->graph.channel = nv10_graph_channel;
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engine->graph.create_context = nv20_graph_create_context;
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engine->graph.destroy_context = nv20_graph_destroy_context;
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engine->graph.fifo_access = nv04_graph_fifo_access;
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engine->graph.load_context = nv20_graph_load_context;
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engine->graph.unload_context = nv20_graph_unload_context;
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engine->graph.object_new = nv04_graph_object_new;
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engine->graph.init = nouveau_stub_init;
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engine->graph.takedown = nouveau_stub_takedown;
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engine->graph.channel = nvc0_graph_channel;
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engine->graph.fifo_access = nvc0_graph_fifo_access;
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engine->graph.set_tile_region = nv20_graph_set_tile_region;
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engine->fifo.channels = 32;
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engine->fifo.init = nv10_fifo_init;
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@ -238,15 +233,10 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
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engine->fb.init_tile_region = nv30_fb_init_tile_region;
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engine->fb.set_tile_region = nv10_fb_set_tile_region;
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engine->fb.free_tile_region = nv30_fb_free_tile_region;
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engine->graph.init = nv30_graph_init;
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engine->graph.takedown = nv20_graph_takedown;
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engine->graph.fifo_access = nv04_graph_fifo_access;
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engine->graph.channel = nv10_graph_channel;
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engine->graph.create_context = nv20_graph_create_context;
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engine->graph.destroy_context = nv20_graph_destroy_context;
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engine->graph.load_context = nv20_graph_load_context;
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engine->graph.unload_context = nv20_graph_unload_context;
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engine->graph.object_new = nv04_graph_object_new;
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engine->graph.init = nouveau_stub_init;
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engine->graph.takedown = nouveau_stub_takedown;
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engine->graph.channel = nvc0_graph_channel;
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engine->graph.fifo_access = nvc0_graph_fifo_access;
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engine->graph.set_tile_region = nv20_graph_set_tile_region;
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engine->fifo.channels = 32;
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engine->fifo.init = nv10_fifo_init;
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@ -614,6 +604,10 @@ nouveau_card_init(struct drm_device *dev)
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goto out_timer;
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switch (dev_priv->card_type) {
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case NV_20:
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case NV_30:
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nv20_graph_create(dev);
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break;
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case NV_40:
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nv40_graph_create(dev);
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break;
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@ -623,6 +617,8 @@ nouveau_card_init(struct drm_device *dev)
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case NV_C0:
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nvc0_graph_create(dev);
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break;
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default:
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break;
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}
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switch (dev_priv->chipset) {
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@ -24,6 +24,14 @@
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*
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*/
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struct nv20_graph_engine {
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struct nouveau_exec_engine base;
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struct nouveau_gpuobj *ctxtab;
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void (*grctx_init)(struct nouveau_gpuobj *);
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u32 grctx_size;
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u32 grctx_user;
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};
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#define NV20_GRCTX_SIZE (3580*4)
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#define NV25_GRCTX_SIZE (3529*4)
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#define NV2A_GRCTX_SIZE (3500*4)
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@ -32,12 +40,54 @@
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#define NV34_GRCTX_SIZE (18140)
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#define NV35_36_GRCTX_SIZE (22396)
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static int nv20_graph_register(struct drm_device *);
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static int nv30_graph_register(struct drm_device *);
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static void nv20_graph_isr(struct drm_device *);
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int
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nv20_graph_unload_context(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
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struct nouveau_channel *chan;
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struct nouveau_gpuobj *grctx;
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u32 tmp;
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chan = nv10_graph_channel(dev);
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if (!chan)
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return 0;
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grctx = chan->engctx[NVOBJ_ENGINE_GR];
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nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, grctx->pinst >> 4);
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nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_XFER,
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NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE);
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nouveau_wait_for_idle(dev);
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nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000000);
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tmp = nv_rd32(dev, NV10_PGRAPH_CTX_USER) & 0x00ffffff;
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tmp |= (pfifo->channels - 1) << 24;
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nv_wr32(dev, NV10_PGRAPH_CTX_USER, tmp);
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return 0;
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}
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static void
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nv20_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
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nv20_graph_rdi(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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int i, writecount = 32;
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uint32_t rdi_index = 0x2c80000;
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if (dev_priv->chipset == 0x20) {
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rdi_index = 0x3d0000;
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writecount = 15;
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}
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nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, rdi_index);
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for (i = 0; i < writecount; i++)
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nv_wr32(dev, NV10_PGRAPH_RDI_DATA, 0);
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nouveau_wait_for_idle(dev);
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}
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static void
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nv20_graph_context_init(struct nouveau_gpuobj *ctx)
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{
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int i;
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@ -87,7 +137,7 @@ nv20_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
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}
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static void
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nv25_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
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nv25_graph_context_init(struct nouveau_gpuobj *ctx)
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{
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int i;
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@ -146,7 +196,7 @@ nv25_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
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}
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static void
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nv2a_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
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nv2a_graph_context_init(struct nouveau_gpuobj *ctx)
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{
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int i;
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@ -196,7 +246,7 @@ nv2a_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
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}
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static void
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nv30_31_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
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nv30_31_graph_context_init(struct nouveau_gpuobj *ctx)
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{
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int i;
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@ -254,7 +304,7 @@ nv30_31_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
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}
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static void
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nv34_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
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nv34_graph_context_init(struct nouveau_gpuobj *ctx)
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{
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int i;
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@ -312,7 +362,7 @@ nv34_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
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}
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static void
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nv35_36_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
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nv35_36_graph_context_init(struct nouveau_gpuobj *ctx)
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{
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int i;
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@ -370,145 +420,54 @@ nv35_36_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
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}
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int
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nv20_graph_create_context(struct nouveau_channel *chan)
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nv20_graph_context_new(struct nouveau_channel *chan, int engine)
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{
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struct nv20_graph_engine *pgraph = nv_engine(chan->dev, engine);
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struct nouveau_gpuobj *grctx = NULL;
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
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void (*ctx_init)(struct drm_device *, struct nouveau_gpuobj *);
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unsigned int idoffs = 0x28;
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int ret;
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switch (dev_priv->chipset) {
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case 0x20:
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ctx_init = nv20_graph_context_init;
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idoffs = 0;
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break;
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case 0x25:
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case 0x28:
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ctx_init = nv25_graph_context_init;
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break;
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case 0x2a:
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ctx_init = nv2a_graph_context_init;
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idoffs = 0;
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break;
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case 0x30:
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case 0x31:
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ctx_init = nv30_31_graph_context_init;
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break;
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case 0x34:
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ctx_init = nv34_graph_context_init;
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break;
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case 0x35:
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case 0x36:
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ctx_init = nv35_36_graph_context_init;
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break;
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default:
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BUG_ON(1);
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}
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ret = nouveau_gpuobj_new(dev, chan, pgraph->grctx_size, 16,
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NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin_grctx);
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ret = nouveau_gpuobj_new(dev, NULL, pgraph->grctx_size, 16,
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NVOBJ_FLAG_ZERO_ALLOC, &grctx);
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if (ret)
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return ret;
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/* Initialise default context values */
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ctx_init(dev, chan->ramin_grctx);
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pgraph->grctx_init(grctx);
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/* nv20: nv_wo32(dev, chan->ramin_grctx->gpuobj, 10, chan->id<<24); */
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nv_wo32(chan->ramin_grctx, idoffs,
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(chan->id << 24) | 0x1); /* CTX_USER */
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/* CTX_USER */
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nv_wo32(grctx, pgraph->grctx_user, (chan->id << 24) | 0x1);
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nv_wo32(pgraph->ctx_table, chan->id * 4, chan->ramin_grctx->pinst >> 4);
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nv_wo32(pgraph->ctxtab, chan->id * 4, grctx->pinst >> 4);
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chan->engctx[engine] = grctx;
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return 0;
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}
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void
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nv20_graph_destroy_context(struct nouveau_channel *chan)
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nv20_graph_context_del(struct nouveau_channel *chan, int engine)
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{
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struct nv20_graph_engine *pgraph = nv_engine(chan->dev, engine);
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struct nouveau_gpuobj *grctx = chan->engctx[engine];
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
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unsigned long flags;
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spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
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pgraph->fifo_access(dev, false);
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nv04_graph_fifo_access(dev, false);
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/* Unload the context if it's the currently active one */
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if (pgraph->channel(dev) == chan)
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pgraph->unload_context(dev);
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if (nv10_graph_channel(dev) == chan)
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nv20_graph_unload_context(dev);
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pgraph->fifo_access(dev, true);
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nv04_graph_fifo_access(dev, true);
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spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
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/* Free the context resources */
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nv_wo32(pgraph->ctx_table, chan->id * 4, 0);
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nouveau_gpuobj_ref(NULL, &chan->ramin_grctx);
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}
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nv_wo32(pgraph->ctxtab, chan->id * 4, 0);
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int
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nv20_graph_load_context(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->dev;
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uint32_t inst;
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if (!chan->ramin_grctx)
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return -EINVAL;
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inst = chan->ramin_grctx->pinst >> 4;
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nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
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nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_XFER,
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NV20_PGRAPH_CHANNEL_CTX_XFER_LOAD);
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nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
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nouveau_wait_for_idle(dev);
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return 0;
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}
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int
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nv20_graph_unload_context(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
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struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
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struct nouveau_channel *chan;
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uint32_t inst, tmp;
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chan = pgraph->channel(dev);
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if (!chan)
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return 0;
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inst = chan->ramin_grctx->pinst >> 4;
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nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
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nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_XFER,
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NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE);
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nouveau_wait_for_idle(dev);
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nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000000);
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tmp = nv_rd32(dev, NV10_PGRAPH_CTX_USER) & 0x00ffffff;
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tmp |= (pfifo->channels - 1) << 24;
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nv_wr32(dev, NV10_PGRAPH_CTX_USER, tmp);
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return 0;
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}
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static void
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nv20_graph_rdi(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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int i, writecount = 32;
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uint32_t rdi_index = 0x2c80000;
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if (dev_priv->chipset == 0x20) {
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rdi_index = 0x3d0000;
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writecount = 15;
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}
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nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, rdi_index);
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for (i = 0; i < writecount; i++)
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nv_wr32(dev, NV10_PGRAPH_RDI_DATA, 0);
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nouveau_wait_for_idle(dev);
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nouveau_gpuobj_ref(NULL, &grctx);
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chan->engctx[engine] = NULL;
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}
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void
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@ -536,56 +495,22 @@ nv20_graph_set_tile_region(struct drm_device *dev, int i)
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}
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int
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nv20_graph_init(struct drm_device *dev)
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nv20_graph_init(struct drm_device *dev, int engine)
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{
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struct nv20_graph_engine *pgraph = nv_engine(dev, engine);
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
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uint32_t tmp, vramsz;
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int ret, i;
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switch (dev_priv->chipset) {
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case 0x20:
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pgraph->grctx_size = NV20_GRCTX_SIZE;
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break;
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case 0x25:
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case 0x28:
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pgraph->grctx_size = NV25_GRCTX_SIZE;
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break;
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case 0x2a:
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pgraph->grctx_size = NV2A_GRCTX_SIZE;
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break;
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default:
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NV_ERROR(dev, "unknown chipset, disabling acceleration\n");
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pgraph->accel_blocked = true;
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return 0;
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}
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int i;
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nv_wr32(dev, NV03_PMC_ENABLE,
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nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PGRAPH);
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nv_wr32(dev, NV03_PMC_ENABLE,
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nv_rd32(dev, NV03_PMC_ENABLE) | NV_PMC_ENABLE_PGRAPH);
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if (!pgraph->ctx_table) {
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/* Create Context Pointer Table */
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ret = nouveau_gpuobj_new(dev, NULL, 32 * 4, 16,
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NVOBJ_FLAG_ZERO_ALLOC,
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&pgraph->ctx_table);
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if (ret)
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return ret;
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}
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nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_TABLE,
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pgraph->ctx_table->pinst >> 4);
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nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_TABLE, pgraph->ctxtab->pinst >> 4);
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nv20_graph_rdi(dev);
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ret = nv20_graph_register(dev);
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if (ret) {
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nouveau_gpuobj_ref(NULL, &pgraph->ctx_table);
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return ret;
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}
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nouveau_irq_register(dev, 12, nv20_graph_isr);
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nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF);
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nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
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|
||||
@ -657,67 +582,20 @@ nv20_graph_init(struct drm_device *dev)
|
||||
return 0;
|
||||
}
|
||||
|
||||
void
|
||||
nv20_graph_takedown(struct drm_device *dev)
|
||||
{
|
||||
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
||||
struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
|
||||
|
||||
nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0x00000000);
|
||||
nouveau_irq_unregister(dev, 12);
|
||||
|
||||
nouveau_gpuobj_ref(NULL, &pgraph->ctx_table);
|
||||
}
|
||||
|
||||
int
|
||||
nv30_graph_init(struct drm_device *dev)
|
||||
nv30_graph_init(struct drm_device *dev, int engine)
|
||||
{
|
||||
struct nv20_graph_engine *pgraph = nv_engine(dev, engine);
|
||||
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
||||
struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
|
||||
int ret, i;
|
||||
|
||||
switch (dev_priv->chipset) {
|
||||
case 0x30:
|
||||
case 0x31:
|
||||
pgraph->grctx_size = NV30_31_GRCTX_SIZE;
|
||||
break;
|
||||
case 0x34:
|
||||
pgraph->grctx_size = NV34_GRCTX_SIZE;
|
||||
break;
|
||||
case 0x35:
|
||||
case 0x36:
|
||||
pgraph->grctx_size = NV35_36_GRCTX_SIZE;
|
||||
break;
|
||||
default:
|
||||
NV_ERROR(dev, "unknown chipset, disabling acceleration\n");
|
||||
pgraph->accel_blocked = true;
|
||||
return 0;
|
||||
}
|
||||
int i;
|
||||
|
||||
nv_wr32(dev, NV03_PMC_ENABLE,
|
||||
nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PGRAPH);
|
||||
nv_wr32(dev, NV03_PMC_ENABLE,
|
||||
nv_rd32(dev, NV03_PMC_ENABLE) | NV_PMC_ENABLE_PGRAPH);
|
||||
|
||||
if (!pgraph->ctx_table) {
|
||||
/* Create Context Pointer Table */
|
||||
ret = nouveau_gpuobj_new(dev, NULL, 32 * 4, 16,
|
||||
NVOBJ_FLAG_ZERO_ALLOC,
|
||||
&pgraph->ctx_table);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_TABLE, pgraph->ctxtab->pinst >> 4);
|
||||
|
||||
ret = nv30_graph_register(dev);
|
||||
if (ret) {
|
||||
nouveau_gpuobj_ref(NULL, &pgraph->ctx_table);
|
||||
return ret;
|
||||
}
|
||||
|
||||
nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_TABLE,
|
||||
pgraph->ctx_table->pinst >> 4);
|
||||
|
||||
nouveau_irq_register(dev, 12, nv20_graph_isr);
|
||||
nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF);
|
||||
nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
|
||||
|
||||
@ -775,85 +653,11 @@ nv30_graph_init(struct drm_device *dev)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
nv20_graph_register(struct drm_device *dev)
|
||||
int
|
||||
nv20_graph_fini(struct drm_device *dev, int engine)
|
||||
{
|
||||
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
||||
|
||||
if (dev_priv->engine.graph.registered)
|
||||
return 0;
|
||||
|
||||
NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
|
||||
NVOBJ_CLASS(dev, 0x0030, GR); /* null */
|
||||
NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
|
||||
NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */
|
||||
NVOBJ_CLASS(dev, 0x009f, GR); /* imageblit (nv12) */
|
||||
NVOBJ_CLASS(dev, 0x008a, GR); /* ifc */
|
||||
NVOBJ_CLASS(dev, 0x0089, GR); /* sifm */
|
||||
NVOBJ_CLASS(dev, 0x0062, GR); /* surf2d */
|
||||
NVOBJ_CLASS(dev, 0x0043, GR); /* rop */
|
||||
NVOBJ_CLASS(dev, 0x0012, GR); /* beta1 */
|
||||
NVOBJ_CLASS(dev, 0x0072, GR); /* beta4 */
|
||||
NVOBJ_CLASS(dev, 0x0019, GR); /* cliprect */
|
||||
NVOBJ_CLASS(dev, 0x0044, GR); /* pattern */
|
||||
NVOBJ_CLASS(dev, 0x009e, GR); /* swzsurf */
|
||||
NVOBJ_CLASS(dev, 0x0096, GR); /* celcius */
|
||||
|
||||
/* kelvin */
|
||||
if (dev_priv->chipset < 0x25)
|
||||
NVOBJ_CLASS(dev, 0x0097, GR);
|
||||
else
|
||||
NVOBJ_CLASS(dev, 0x0597, GR);
|
||||
|
||||
/* nvsw */
|
||||
NVOBJ_CLASS(dev, 0x506e, SW);
|
||||
NVOBJ_MTHD (dev, 0x506e, 0x0500, nv04_graph_mthd_page_flip);
|
||||
|
||||
dev_priv->engine.graph.registered = true;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
nv30_graph_register(struct drm_device *dev)
|
||||
{
|
||||
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
||||
|
||||
if (dev_priv->engine.graph.registered)
|
||||
return 0;
|
||||
|
||||
NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
|
||||
NVOBJ_CLASS(dev, 0x0030, GR); /* null */
|
||||
NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
|
||||
NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */
|
||||
NVOBJ_CLASS(dev, 0x009f, GR); /* imageblit (nv12) */
|
||||
NVOBJ_CLASS(dev, 0x008a, GR); /* ifc */
|
||||
NVOBJ_CLASS(dev, 0x038a, GR); /* ifc (nv30) */
|
||||
NVOBJ_CLASS(dev, 0x0089, GR); /* sifm */
|
||||
NVOBJ_CLASS(dev, 0x0389, GR); /* sifm (nv30) */
|
||||
NVOBJ_CLASS(dev, 0x0062, GR); /* surf2d */
|
||||
NVOBJ_CLASS(dev, 0x0362, GR); /* surf2d (nv30) */
|
||||
NVOBJ_CLASS(dev, 0x0043, GR); /* rop */
|
||||
NVOBJ_CLASS(dev, 0x0012, GR); /* beta1 */
|
||||
NVOBJ_CLASS(dev, 0x0072, GR); /* beta4 */
|
||||
NVOBJ_CLASS(dev, 0x0019, GR); /* cliprect */
|
||||
NVOBJ_CLASS(dev, 0x0044, GR); /* pattern */
|
||||
NVOBJ_CLASS(dev, 0x039e, GR); /* swzsurf */
|
||||
|
||||
/* rankine */
|
||||
if (0x00000003 & (1 << (dev_priv->chipset & 0x0f)))
|
||||
NVOBJ_CLASS(dev, 0x0397, GR);
|
||||
else
|
||||
if (0x00000010 & (1 << (dev_priv->chipset & 0x0f)))
|
||||
NVOBJ_CLASS(dev, 0x0697, GR);
|
||||
else
|
||||
if (0x000001e0 & (1 << (dev_priv->chipset & 0x0f)))
|
||||
NVOBJ_CLASS(dev, 0x0497, GR);
|
||||
|
||||
/* nvsw */
|
||||
NVOBJ_CLASS(dev, 0x506e, SW);
|
||||
NVOBJ_MTHD (dev, 0x506e, 0x0500, nv04_graph_mthd_page_flip);
|
||||
|
||||
dev_priv->engine.graph.registered = true;
|
||||
nv20_graph_unload_context(dev);
|
||||
nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0x00000000);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -897,3 +701,136 @@ nv20_graph_isr(struct drm_device *dev)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
nv20_graph_destroy(struct drm_device *dev, int engine)
|
||||
{
|
||||
struct nv20_graph_engine *pgraph = nv_engine(dev, engine);
|
||||
|
||||
nouveau_irq_unregister(dev, 12);
|
||||
nouveau_gpuobj_ref(NULL, &pgraph->ctxtab);
|
||||
|
||||
NVOBJ_ENGINE_DEL(dev, GR);
|
||||
kfree(pgraph);
|
||||
}
|
||||
|
||||
int
|
||||
nv20_graph_create(struct drm_device *dev)
|
||||
{
|
||||
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
||||
struct nv20_graph_engine *pgraph;
|
||||
int ret;
|
||||
|
||||
pgraph = kzalloc(sizeof(*pgraph), GFP_KERNEL);
|
||||
if (!pgraph)
|
||||
return -ENOMEM;
|
||||
|
||||
pgraph->base.destroy = nv20_graph_destroy;
|
||||
pgraph->base.fini = nv20_graph_fini;
|
||||
pgraph->base.context_new = nv20_graph_context_new;
|
||||
pgraph->base.context_del = nv20_graph_context_del;
|
||||
pgraph->base.object_new = nv04_graph_object_new;
|
||||
|
||||
pgraph->grctx_user = 0x0028;
|
||||
if (dev_priv->card_type == NV_20) {
|
||||
pgraph->base.init = nv20_graph_init;
|
||||
switch (dev_priv->chipset) {
|
||||
case 0x20:
|
||||
pgraph->grctx_init = nv20_graph_context_init;
|
||||
pgraph->grctx_size = NV20_GRCTX_SIZE;
|
||||
pgraph->grctx_user = 0x0000;
|
||||
break;
|
||||
case 0x25:
|
||||
case 0x28:
|
||||
pgraph->grctx_init = nv25_graph_context_init;
|
||||
pgraph->grctx_size = NV25_GRCTX_SIZE;
|
||||
break;
|
||||
case 0x2a:
|
||||
pgraph->grctx_init = nv2a_graph_context_init;
|
||||
pgraph->grctx_size = NV2A_GRCTX_SIZE;
|
||||
pgraph->grctx_user = 0x0000;
|
||||
break;
|
||||
default:
|
||||
NV_ERROR(dev, "unknown nv20, disabling acceleration\n");
|
||||
dev_priv->engine.graph.accel_blocked = true;
|
||||
return 0;
|
||||
}
|
||||
} else {
|
||||
pgraph->base.init = nv30_graph_init;
|
||||
switch (dev_priv->chipset) {
|
||||
case 0x30:
|
||||
case 0x31:
|
||||
pgraph->grctx_init = nv30_31_graph_context_init;
|
||||
pgraph->grctx_size = NV30_31_GRCTX_SIZE;
|
||||
break;
|
||||
case 0x34:
|
||||
pgraph->grctx_init = nv34_graph_context_init;
|
||||
pgraph->grctx_size = NV34_GRCTX_SIZE;
|
||||
break;
|
||||
case 0x35:
|
||||
case 0x36:
|
||||
pgraph->grctx_init = nv35_36_graph_context_init;
|
||||
pgraph->grctx_size = NV35_36_GRCTX_SIZE;
|
||||
break;
|
||||
default:
|
||||
NV_ERROR(dev, "unknown nv30, disabling acceleration\n");
|
||||
dev_priv->engine.graph.accel_blocked = true;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
/* Create Context Pointer Table */
|
||||
ret = nouveau_gpuobj_new(dev, NULL, 32 * 4, 16, NVOBJ_FLAG_ZERO_ALLOC,
|
||||
&pgraph->ctxtab);
|
||||
if (ret) {
|
||||
kfree(pgraph);
|
||||
return ret;
|
||||
}
|
||||
|
||||
NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base);
|
||||
nouveau_irq_register(dev, 12, nv20_graph_isr);
|
||||
|
||||
/* nvsw */
|
||||
NVOBJ_CLASS(dev, 0x506e, SW);
|
||||
NVOBJ_MTHD (dev, 0x506e, 0x0500, nv04_graph_mthd_page_flip);
|
||||
|
||||
NVOBJ_CLASS(dev, 0x0030, GR); /* null */
|
||||
NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
|
||||
NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */
|
||||
NVOBJ_CLASS(dev, 0x009f, GR); /* imageblit (nv12) */
|
||||
NVOBJ_CLASS(dev, 0x008a, GR); /* ifc */
|
||||
NVOBJ_CLASS(dev, 0x0089, GR); /* sifm */
|
||||
NVOBJ_CLASS(dev, 0x0062, GR); /* surf2d */
|
||||
NVOBJ_CLASS(dev, 0x0043, GR); /* rop */
|
||||
NVOBJ_CLASS(dev, 0x0012, GR); /* beta1 */
|
||||
NVOBJ_CLASS(dev, 0x0072, GR); /* beta4 */
|
||||
NVOBJ_CLASS(dev, 0x0019, GR); /* cliprect */
|
||||
NVOBJ_CLASS(dev, 0x0044, GR); /* pattern */
|
||||
if (dev_priv->card_type == NV_20) {
|
||||
NVOBJ_CLASS(dev, 0x009e, GR); /* swzsurf */
|
||||
NVOBJ_CLASS(dev, 0x0096, GR); /* celcius */
|
||||
|
||||
/* kelvin */
|
||||
if (dev_priv->chipset < 0x25)
|
||||
NVOBJ_CLASS(dev, 0x0097, GR);
|
||||
else
|
||||
NVOBJ_CLASS(dev, 0x0597, GR);
|
||||
} else {
|
||||
NVOBJ_CLASS(dev, 0x038a, GR); /* ifc (nv30) */
|
||||
NVOBJ_CLASS(dev, 0x0389, GR); /* sifm (nv30) */
|
||||
NVOBJ_CLASS(dev, 0x0362, GR); /* surf2d (nv30) */
|
||||
NVOBJ_CLASS(dev, 0x039e, GR); /* swzsurf */
|
||||
|
||||
/* rankine */
|
||||
if (0x00000003 & (1 << (dev_priv->chipset & 0x0f)))
|
||||
NVOBJ_CLASS(dev, 0x0397, GR);
|
||||
else
|
||||
if (0x00000010 & (1 << (dev_priv->chipset & 0x0f)))
|
||||
NVOBJ_CLASS(dev, 0x0697, GR);
|
||||
else
|
||||
if (0x000001e0 & (1 << (dev_priv->chipset & 0x0f)))
|
||||
NVOBJ_CLASS(dev, 0x0497, GR);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user