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kbuild: linguistic fixes for Documentation/kbuild/makefiles.txt
I have done a look-through through Documentation/kbuild/ and my corrections (proposed) are attached. Cc'ed are original author Michael (responsible for comitting changes to these files?), Sam (kbuild maintainer), Adrian (-trivial maintainer). Signed-off-by: Jan Engelhardt <jengelh@gmx.de> Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
This commit is contained in:
Jan Engelhardt
Sam Ravnborg
parent
d9a7ff6646
commit
a07f6033ca
@ -86,7 +86,7 @@ any kernel Makefiles (or any other source files).
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*Normal developers* are people who work on features such as device
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drivers, file systems, and network protocols. These people need to
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maintain the kbuild Makefiles for the subsystem that they are
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maintain the kbuild Makefiles for the subsystem they are
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working on. In order to do this effectively, they need some overall
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knowledge about the kernel Makefiles, plus detailed knowledge about the
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public interface for kbuild.
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@ -104,10 +104,10 @@ This document is aimed towards normal developers and arch developers.
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=== 3 The kbuild files
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Most Makefiles within the kernel are kbuild Makefiles that use the
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kbuild infrastructure. This chapter introduce the syntax used in the
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kbuild infrastructure. This chapter introduces the syntax used in the
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kbuild makefiles.
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The preferred name for the kbuild files are 'Makefile' but 'Kbuild' can
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be used and if both a 'Makefile' and a 'Kbuild' file exists then the 'Kbuild'
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be used and if both a 'Makefile' and a 'Kbuild' file exists, then the 'Kbuild'
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file will be used.
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Section 3.1 "Goal definitions" is a quick intro, further chapters provide
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@ -124,7 +124,7 @@ more details, with real examples.
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Example:
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obj-y += foo.o
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This tell kbuild that there is one object in that directory named
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This tell kbuild that there is one object in that directory, named
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foo.o. foo.o will be built from foo.c or foo.S.
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If foo.o shall be built as a module, the variable obj-m is used.
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@ -140,7 +140,7 @@ more details, with real examples.
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--- 3.2 Built-in object goals - obj-y
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The kbuild Makefile specifies object files for vmlinux
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in the lists $(obj-y). These lists depend on the kernel
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in the $(obj-y) lists. These lists depend on the kernel
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configuration.
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Kbuild compiles all the $(obj-y) files. It then calls
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@ -154,8 +154,8 @@ more details, with real examples.
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Link order is significant, because certain functions
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(module_init() / __initcall) will be called during boot in the
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order they appear. So keep in mind that changing the link
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order may e.g. change the order in which your SCSI
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controllers are detected, and thus you disks are renumbered.
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order may e.g. change the order in which your SCSI
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controllers are detected, and thus your disks are renumbered.
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Example:
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#drivers/isdn/i4l/Makefile
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@ -206,8 +206,8 @@ more details, with real examples.
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ext2-y := balloc.o bitmap.o
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ext2-$(CONFIG_EXT2_FS_XATTR) += xattr.o
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In this example xattr.o is only part of the composite object
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ext2.o, if $(CONFIG_EXT2_FS_XATTR) evaluates to 'y'.
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In this example, xattr.o is only part of the composite object
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ext2.o if $(CONFIG_EXT2_FS_XATTR) evaluates to 'y'.
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Note: Of course, when you are building objects into the kernel,
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the syntax above will also work. So, if you have CONFIG_EXT2_FS=y,
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@ -221,16 +221,16 @@ more details, with real examples.
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--- 3.5 Library file goals - lib-y
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Objects listed with obj-* are used for modules or
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Objects listed with obj-* are used for modules, or
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combined in a built-in.o for that specific directory.
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There is also the possibility to list objects that will
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be included in a library, lib.a.
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All objects listed with lib-y are combined in a single
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library for that directory.
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Objects that are listed in obj-y and additional listed in
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Objects that are listed in obj-y and additionaly listed in
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lib-y will not be included in the library, since they will anyway
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be accessible.
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For consistency objects listed in lib-m will be included in lib.a.
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For consistency, objects listed in lib-m will be included in lib.a.
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Note that the same kbuild makefile may list files to be built-in
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and to be part of a library. Therefore the same directory
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@ -241,11 +241,11 @@ more details, with real examples.
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lib-y := checksum.o delay.o
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This will create a library lib.a based on checksum.o and delay.o.
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For kbuild to actually recognize that there is a lib.a being build
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For kbuild to actually recognize that there is a lib.a being built,
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the directory shall be listed in libs-y.
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See also "6.3 List directories to visit when descending".
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Usage of lib-y is normally restricted to lib/ and arch/*/lib.
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Use of lib-y is normally restricted to lib/ and arch/*/lib.
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--- 3.6 Descending down in directories
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@ -255,7 +255,7 @@ more details, with real examples.
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invoke make recursively in subdirectories, provided you let it know of
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them.
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To do so obj-y and obj-m are used.
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To do so, obj-y and obj-m are used.
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ext2 lives in a separate directory, and the Makefile present in fs/
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tells kbuild to descend down using the following assignment.
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@ -353,8 +353,8 @@ more details, with real examples.
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Special rules are used when the kbuild infrastructure does
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not provide the required support. A typical example is
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header files generated during the build process.
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Another example is the architecture specific Makefiles which
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needs special rules to prepare boot images etc.
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Another example are the architecture specific Makefiles which
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need special rules to prepare boot images etc.
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Special rules are written as normal Make rules.
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Kbuild is not executing in the directory where the Makefile is
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@ -387,22 +387,22 @@ more details, with real examples.
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--- 3.11 $(CC) support functions
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The kernel may be build with several different versions of
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The kernel may be built with several different versions of
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$(CC), each supporting a unique set of features and options.
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kbuild provide basic support to check for valid options for $(CC).
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$(CC) is useally the gcc compiler, but other alternatives are
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available.
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as-option
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as-option is used to check if $(CC) when used to compile
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assembler (*.S) files supports the given option. An optional
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second option may be specified if first option are not supported.
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as-option is used to check if $(CC) -- when used to compile
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assembler (*.S) files -- supports the given option. An optional
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second option may be specified if the first option is not supported.
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Example:
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#arch/sh/Makefile
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cflags-y += $(call as-option,-Wa$(comma)-isa=$(isa-y),)
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In the above example cflags-y will be assinged the the option
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In the above example, cflags-y will be assigned the option
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-Wa$(comma)-isa=$(isa-y) if it is supported by $(CC).
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The second argument is optional, and if supplied will be used
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if first argument is not supported.
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@ -422,7 +422,7 @@ more details, with real examples.
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if first argument is not supported.
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cc-option
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cc-option is used to check if $(CC) support a given option, and not
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cc-option is used to check if $(CC) supports a given option, and not
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supported to use an optional second option.
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Example:
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@ -430,8 +430,8 @@ more details, with real examples.
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cflags-y += $(call cc-option,-march=pentium-mmx,-march=i586)
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In the above example cflags-y will be assigned the option
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-march=pentium-mmx if supported by $(CC), otherwise -march-i586.
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The second argument to cc-option is optional, and if omitted
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-march=pentium-mmx if supported by $(CC), otherwise -march=i586.
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The second argument to cc-option is optional, and if omitted,
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cflags-y will be assigned no value if first option is not supported.
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cc-option-yn
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@ -444,14 +444,15 @@ more details, with real examples.
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aflags-$(biarch) += -a32
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cflags-$(biarch) += -m32
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In the above example $(biarch) is set to y if $(CC) supports the -m32
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option. When $(biarch) equals to y the expanded variables $(aflags-y)
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and $(cflags-y) will be assigned the values -a32 and -m32.
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In the above example, $(biarch) is set to y if $(CC) supports the -m32
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option. When $(biarch) equals 'y', the expanded variables $(aflags-y)
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and $(cflags-y) will be assigned the values -a32 and -m32,
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respectively.
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cc-option-align
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gcc version >= 3.0 shifted type of options used to speify
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alignment of functions, loops etc. $(cc-option-align) whrn used
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as prefix to the align options will select the right prefix:
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gcc versions >= 3.0 changed the type of options used to specify
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alignment of functions, loops etc. $(cc-option-align), when used
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as prefix to the align options, will select the right prefix:
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gcc < 3.00
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cc-option-align = -malign
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gcc >= 3.00
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@ -460,15 +461,15 @@ more details, with real examples.
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Example:
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CFLAGS += $(cc-option-align)-functions=4
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In the above example the option -falign-functions=4 is used for
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gcc >= 3.00. For gcc < 3.00 -malign-functions=4 is used.
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In the above example, the option -falign-functions=4 is used for
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gcc >= 3.00. For gcc < 3.00, -malign-functions=4 is used.
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cc-version
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cc-version return a numerical version of the $(CC) compiler version.
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cc-version returns a numerical version of the $(CC) compiler version.
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The format is <major><minor> where both are two digits. So for example
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gcc 3.41 would return 0341.
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cc-version is useful when a specific $(CC) version is faulty in one
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area, for example the -mregparm=3 were broken in some gcc version
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area, for example -mregparm=3 was broken in some gcc versions
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even though the option was accepted by gcc.
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Example:
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@ -477,18 +478,18 @@ more details, with real examples.
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if [ $(call cc-version) -ge 0300 ] ; then \
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echo "-mregparm=3"; fi ;)
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In the above example -mregparm=3 is only used for gcc version greater
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In the above example, -mregparm=3 is only used for gcc version greater
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than or equal to gcc 3.0.
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cc-ifversion
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cc-ifversion test the version of $(CC) and equals last argument if
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cc-ifversion tests the version of $(CC) and equals last argument if
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version expression is true.
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Example:
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#fs/reiserfs/Makefile
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EXTRA_CFLAGS := $(call cc-ifversion, -lt, 0402, -O1)
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In this example EXTRA_CFLAGS will be assigned the value -O1 if the
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In this example, EXTRA_CFLAGS will be assigned the value -O1 if the
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$(CC) version is less than 4.2.
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cc-ifversion takes all the shell operators:
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-eq, -ne, -lt, -le, -gt, and -ge
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@ -529,7 +530,7 @@ Both possibilities are described in the following.
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Host programs can be made up based on composite objects.
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The syntax used to define composite objects for host programs is
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similar to the syntax used for kernel objects.
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$(<executeable>-objs) list all objects used to link the final
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$(<executeable>-objs) lists all objects used to link the final
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executable.
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Example:
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@ -538,9 +539,9 @@ Both possibilities are described in the following.
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lxdialog-objs := checklist.o lxdialog.o
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Objects with extension .o are compiled from the corresponding .c
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files. In the above example checklist.c is compiled to checklist.o
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files. In the above example, checklist.c is compiled to checklist.o
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and lxdialog.c is compiled to lxdialog.o.
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Finally the two .o files are linked to the executable, lxdialog.
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Finally, the two .o files are linked to the executable, lxdialog.
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Note: The syntax <executable>-y is not permitted for host-programs.
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--- 4.3 Defining shared libraries
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@ -594,7 +595,7 @@ Both possibilities are described in the following.
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The programs will always be compiled utilising $(HOSTCC) passed
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the options specified in $(HOSTCFLAGS).
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To set flags that will take effect for all host programs created
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in that Makefile use the variable HOST_EXTRACFLAGS.
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in that Makefile, use the variable HOST_EXTRACFLAGS.
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Example:
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#scripts/lxdialog/Makefile
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@ -613,7 +614,8 @@ Both possibilities are described in the following.
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#scripts/kconfig/Makefile
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HOSTLOADLIBES_qconf := -L$(QTDIR)/lib
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When linking qconf it will be passed the extra option "-L$(QTDIR)/lib".
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When linking qconf, it will be passed the extra option
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"-L$(QTDIR)/lib".
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--- 4.6 When host programs are actually built
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@ -648,7 +650,7 @@ Both possibilities are described in the following.
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--- 4.7 Using hostprogs-$(CONFIG_FOO)
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A typcal pattern in a Kbuild file lok like this:
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A typcal pattern in a Kbuild file looks like this:
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Example:
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#scripts/Makefile
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@ -656,13 +658,13 @@ Both possibilities are described in the following.
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Kbuild knows about both 'y' for built-in and 'm' for module.
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So if a config symbol evaluate to 'm', kbuild will still build
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the binary. In other words Kbuild handle hostprogs-m exactly
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like hostprogs-y. But only hostprogs-y is recommend used
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when no CONFIG symbol are involved.
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the binary. In other words, Kbuild handles hostprogs-m exactly
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like hostprogs-y. But only hostprogs-y is recommended to be used
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when no CONFIG symbols are involved.
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=== 5 Kbuild clean infrastructure
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"make clean" deletes most generated files in the src tree where the kernel
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"make clean" deletes most generated files in the obj tree where the kernel
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is compiled. This includes generated files such as host programs.
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Kbuild knows targets listed in $(hostprogs-y), $(hostprogs-m), $(always),
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$(extra-y) and $(targets). They are all deleted during "make clean".
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@ -723,29 +725,29 @@ be visited during "make clean".
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The top level Makefile sets up the environment and does the preparation,
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before starting to descend down in the individual directories.
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The top level makefile contains the generic part, whereas the
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arch/$(ARCH)/Makefile contains what is required to set-up kbuild
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to the said architecture.
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To do so arch/$(ARCH)/Makefile sets a number of variables, and defines
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The top level makefile contains the generic part, whereas
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arch/$(ARCH)/Makefile contains what is required to set up kbuild
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for said architecture.
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To do so, arch/$(ARCH)/Makefile sets up a number of variables and defines
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a few targets.
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When kbuild executes the following steps are followed (roughly):
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1) Configuration of the kernel => produced .config
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When kbuild executes, the following steps are followed (roughly):
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1) Configuration of the kernel => produce .config
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2) Store kernel version in include/linux/version.h
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3) Symlink include/asm to include/asm-$(ARCH)
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4) Updating all other prerequisites to the target prepare:
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- Additional prerequisites are specified in arch/$(ARCH)/Makefile
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5) Recursively descend down in all directories listed in
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init-* core* drivers-* net-* libs-* and build all targets.
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- The value of the above variables are extended in arch/$(ARCH)/Makefile.
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- The values of the above variables are expanded in arch/$(ARCH)/Makefile.
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6) All object files are then linked and the resulting file vmlinux is
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located at the root of the src tree.
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located at the root of the obj tree.
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The very first objects linked are listed in head-y, assigned by
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arch/$(ARCH)/Makefile.
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7) Finally the architecture specific part does any required post processing
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7) Finally, the architecture specific part does any required post processing
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and builds the final bootimage.
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- This includes building boot records
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- Preparing initrd images and the like
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- Preparing initrd images and thelike
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--- 6.1 Set variables to tweak the build to the architecture
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@ -770,7 +772,7 @@ When kbuild executes the following steps are followed (roughly):
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LDFLAGS_vmlinux Options for $(LD) when linking vmlinux
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LDFLAGS_vmlinux is used to specify additional flags to pass to
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the linker when linking the final vmlinux.
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the linker when linking the final vmlinux image.
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LDFLAGS_vmlinux uses the LDFLAGS_$@ support.
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Example:
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@ -780,7 +782,7 @@ When kbuild executes the following steps are followed (roughly):
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OBJCOPYFLAGS objcopy flags
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When $(call if_changed,objcopy) is used to translate a .o file,
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then the flags specified in OBJCOPYFLAGS will be used.
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the flags specified in OBJCOPYFLAGS will be used.
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$(call if_changed,objcopy) is often used to generate raw binaries on
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vmlinux.
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@ -792,7 +794,7 @@ When kbuild executes the following steps are followed (roughly):
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$(obj)/image: vmlinux FORCE
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$(call if_changed,objcopy)
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In this example the binary $(obj)/image is a binary version of
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In this example, the binary $(obj)/image is a binary version of
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vmlinux. The usage of $(call if_changed,xxx) will be described later.
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AFLAGS $(AS) assembler flags
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@ -809,7 +811,7 @@ When kbuild executes the following steps are followed (roughly):
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Default value - see top level Makefile
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Append or modify as required per architecture.
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Often the CFLAGS variable depends on the configuration.
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Often, the CFLAGS variable depends on the configuration.
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Example:
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#arch/i386/Makefile
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@ -830,7 +832,7 @@ When kbuild executes the following steps are followed (roughly):
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...
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The first examples utilises the trick that a config option expands
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The first example utilises the trick that a config option expands
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to 'y' when selected.
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CFLAGS_KERNEL $(CC) options specific for built-in
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@ -846,15 +848,15 @@ When kbuild executes the following steps are followed (roughly):
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--- 6.2 Add prerequisites to archprepare:
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The archprepare: rule is used to list prerequisites that needs to be
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The archprepare: rule is used to list prerequisites that need to be
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built before starting to descend down in the subdirectories.
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This is usual header files containing assembler constants.
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This is usually used for header files containing assembler constants.
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Example:
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#arch/arm/Makefile
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archprepare: maketools
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In this example the file target maketools will be processed
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In this example, the file target maketools will be processed
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before descending down in the subdirectories.
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See also chapter XXX-TODO that describe how kbuild supports
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generating offset header files.
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@ -870,15 +872,16 @@ When kbuild executes the following steps are followed (roughly):
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head-y, init-y, core-y, libs-y, drivers-y, net-y
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$(head-y) list objects to be linked first in vmlinux.
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$(libs-y) list directories where a lib.a archive can be located.
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The rest list directories where a built-in.o object file can be located.
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$(head-y) lists objects to be linked first in vmlinux.
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$(libs-y) lists directories where a lib.a archive can be located.
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The rest lists directories where a built-in.o object file can be
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located.
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$(init-y) objects will be located after $(head-y).
|
||||
Then the rest follows in this order:
|
||||
$(core-y), $(libs-y), $(drivers-y) and $(net-y).
|
||||
|
||||
The top level Makefile define values for all generic directories,
|
||||
The top level Makefile defines values for all generic directories,
|
||||
and arch/$(ARCH)/Makefile only adds architecture specific directories.
|
||||
|
||||
Example:
|
||||
@ -915,9 +918,9 @@ When kbuild executes the following steps are followed (roughly):
|
||||
"$(Q)$(MAKE) $(build)=<dir>" is the recommended way to invoke
|
||||
make in a subdirectory.
|
||||
|
||||
There are no rules for naming of the architecture specific targets,
|
||||
There are no rules for naming architecture specific targets,
|
||||
but executing "make help" will list all relevant targets.
|
||||
To support this $(archhelp) must be defined.
|
||||
To support this, $(archhelp) must be defined.
|
||||
|
||||
Example:
|
||||
#arch/i386/Makefile
|
||||
@ -928,8 +931,8 @@ When kbuild executes the following steps are followed (roughly):
|
||||
When make is executed without arguments, the first goal encountered
|
||||
will be built. In the top level Makefile the first goal present
|
||||
is all:.
|
||||
An architecture shall always per default build a bootable image.
|
||||
In "make help" the default goal is highlighted with a '*'.
|
||||
An architecture shall always, per default, build a bootable image.
|
||||
In "make help", the default goal is highlighted with a '*'.
|
||||
Add a new prerequisite to all: to select a default goal different
|
||||
from vmlinux.
|
||||
|
||||
@ -955,7 +958,7 @@ When kbuild executes the following steps are followed (roughly):
|
||||
#arch/i386/kernel/Makefile
|
||||
extra-y := head.o init_task.o
|
||||
|
||||
In this example extra-y is used to list object files that
|
||||
In this example, extra-y is used to list object files that
|
||||
shall be built, but shall not be linked as part of built-in.o.
|
||||
|
||||
|
||||
@ -972,8 +975,8 @@ When kbuild executes the following steps are followed (roughly):
|
||||
target: source(s) FORCE
|
||||
$(call if_changed,ld/objcopy/gzip)
|
||||
|
||||
When the rule is evaluated it is checked to see if any files
|
||||
needs an update, or the commandline has changed since last
|
||||
When the rule is evaluated, it is checked to see if any files
|
||||
needs an update, or the command line has changed since the last
|
||||
invocation. The latter will force a rebuild if any options
|
||||
to the executable have changed.
|
||||
Any target that utilises if_changed must be listed in $(targets),
|
||||
@ -991,7 +994,7 @@ When kbuild executes the following steps are followed (roughly):
|
||||
#WRONG!# $(call if_changed, ld/objcopy/gzip)
|
||||
|
||||
ld
|
||||
Link target. Often LDFLAGS_$@ is used to set specific options to ld.
|
||||
Link target. Often, LDFLAGS_$@ is used to set specific options to ld.
|
||||
|
||||
objcopy
|
||||
Copy binary. Uses OBJCOPYFLAGS usually specified in
|
||||
@ -1010,10 +1013,10 @@ When kbuild executes the following steps are followed (roughly):
|
||||
$(obj)/setup $(obj)/bootsect: %: %.o FORCE
|
||||
$(call if_changed,ld)
|
||||
|
||||
In this example there are two possible targets, requiring different
|
||||
options to the linker. the linker options are specified using the
|
||||
In this example, there are two possible targets, requiring different
|
||||
options to the linker. The linker options are specified using the
|
||||
LDFLAGS_$@ syntax - one for each potential target.
|
||||
$(targets) are assinged all potential targets, herby kbuild knows
|
||||
$(targets) are assinged all potential targets, by which kbuild knows
|
||||
the targets and will:
|
||||
1) check for commandline changes
|
||||
2) delete target during make clean
|
||||
@ -1027,7 +1030,7 @@ When kbuild executes the following steps are followed (roughly):
|
||||
|
||||
--- 6.7 Custom kbuild commands
|
||||
|
||||
When kbuild is executing with KBUILD_VERBOSE=0 then only a shorthand
|
||||
When kbuild is executing with KBUILD_VERBOSE=0, then only a shorthand
|
||||
of a command is normally displayed.
|
||||
To enable this behaviour for custom commands kbuild requires
|
||||
two variables to be set:
|
||||
@ -1045,7 +1048,7 @@ When kbuild executes the following steps are followed (roughly):
|
||||
$(call if_changed,image)
|
||||
@echo 'Kernel: $@ is ready'
|
||||
|
||||
When updating the $(obj)/bzImage target the line:
|
||||
When updating the $(obj)/bzImage target, the line
|
||||
|
||||
BUILD arch/i386/boot/bzImage
|
||||
|
||||
@ -1054,11 +1057,11 @@ When kbuild executes the following steps are followed (roughly):
|
||||
|
||||
--- 6.8 Preprocessing linker scripts
|
||||
|
||||
When the vmlinux image is build the linker script:
|
||||
When the vmlinux image is built, the linker script
|
||||
arch/$(ARCH)/kernel/vmlinux.lds is used.
|
||||
The script is a preprocessed variant of the file vmlinux.lds.S
|
||||
located in the same directory.
|
||||
kbuild knows .lds file and includes a rule *lds.S -> *lds.
|
||||
kbuild knows .lds files and includes a rule *lds.S -> *lds.
|
||||
|
||||
Example:
|
||||
#arch/i386/kernel/Makefile
|
||||
@ -1068,11 +1071,11 @@ When kbuild executes the following steps are followed (roughly):
|
||||
export CPPFLAGS_vmlinux.lds += -P -C -U$(ARCH)
|
||||
|
||||
The assigment to $(always) is used to tell kbuild to build the
|
||||
target: vmlinux.lds.
|
||||
The assignment to $(CPPFLAGS_vmlinux.lds) tell kbuild to use the
|
||||
target vmlinux.lds.
|
||||
The assignment to $(CPPFLAGS_vmlinux.lds) tells kbuild to use the
|
||||
specified options when building the target vmlinux.lds.
|
||||
|
||||
When building the *.lds target kbuild used the variakles:
|
||||
When building the *.lds target, kbuild uses the variables:
|
||||
CPPFLAGS : Set in top-level Makefile
|
||||
EXTRA_CPPFLAGS : May be set in the kbuild makefile
|
||||
CPPFLAGS_$(@F) : Target specific flags.
|
||||
@ -1147,7 +1150,7 @@ The top Makefile exports the following variables:
|
||||
|
||||
=== 8 Makefile language
|
||||
|
||||
The kernel Makefiles are designed to run with GNU Make. The Makefiles
|
||||
The kernel Makefiles are designed to be run with GNU Make. The Makefiles
|
||||
use only the documented features of GNU Make, but they do use many
|
||||
GNU extensions.
|
||||
|
||||
@ -1169,10 +1172,11 @@ is the right choice.
|
||||
Original version made by Michael Elizabeth Chastain, <mailto:mec@shout.net>
|
||||
Updates by Kai Germaschewski <kai@tp1.ruhr-uni-bochum.de>
|
||||
Updates by Sam Ravnborg <sam@ravnborg.org>
|
||||
Language QA by Jan Engelhardt <jengelh@gmx.de>
|
||||
|
||||
=== 10 TODO
|
||||
|
||||
- Describe how kbuild support shipped files with _shipped.
|
||||
- Describe how kbuild supports shipped files with _shipped.
|
||||
- Generating offset header files.
|
||||
- Add more variables to section 7?
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user