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arm64: dts: ti: k3-am62: Add GPMC and ELM nodes

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Add GPMC and ELM device tree nodes for AM62 SoC family.

Signed-off-by: Nitin Yadav <n-yadav@ti.com>
Signed-off-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20240622-am62lp-sk-nand-v1-1-caee496eaf42@kernel.org
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
This commit is contained in:
Nitin Yadav 2024-06-22 14:59:56 +03:00 committed by Vignesh Raghavendra
parent 3a36c535df
commit a0286c7bf0
2 changed files with 31 additions and 0 deletions
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29
arch/arm64/boot/dts/ti/k3-am62-main.dtsi
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@ -1053,4 +1053,33 @@
status = "disabled";
};
gpmc0: memory-controller@3b000000 {
compatible = "ti,am64-gpmc";
power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 80 0>;
clock-names = "fck";
reg = <0x00 0x03b000000 0x00 0x400>,
<0x00 0x050000000 0x00 0x8000000>;
reg-names = "cfg", "data";
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
gpmc,num-cs = <3>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#size-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
elm0: ecc@25010000 {
compatible = "ti,am64-elm";
reg = <0x00 0x25010000 0x00 0x2000>;
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 54 0>;
clock-names = "fck";
status = "disabled";
};
};

2
arch/arm64/boot/dts/ti/k3-am62.dtsi
View File

@ -68,11 +68,13 @@
<0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
<0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
<0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
<0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */
<0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
<0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
<0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
<0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
<0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */
<0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */
<0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
<0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
<0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */