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net: ethernet: mediatek: Extend SGMII related functions
Add SGMII related logic into a separate file, and also provides options for forcing 1G, 2.5, AN mode for the target PHY, that can be determined from SGMII node in DTS. Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Sean Wang
David S. Miller
parent
3277fc683a
commit
9ffee4a827
@ -3,4 +3,4 @@
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# Makefile for the Mediatek SoCs built-in ethernet macs
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#
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obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth_soc.o
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obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth_soc.o mtk_sgmii.o
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@ -165,36 +165,37 @@ static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed)
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mtk_w32(eth, val, TRGMII_TCK_CTRL);
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}
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static void mtk_gmac_sgmii_hw_setup(struct mtk_eth *eth, int mac_id)
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static int mtk_gmac_sgmii_hw_setup(struct mtk_eth *eth, int mac_id)
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{
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int sid, err;
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u32 val;
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/* Setup the link timer and QPHY power up inside SGMIISYS */
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regmap_write(eth->sgmiisys, SGMSYS_PCS_LINK_TIMER,
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SGMII_LINK_TIMER_DEFAULT);
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/* Enable GMAC with SGMII once we finish the SGMII setup. */
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regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
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val &= ~SYSCFG0_SGMII_MASK;
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regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
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regmap_read(eth->sgmiisys, SGMSYS_SGMII_MODE, &val);
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val |= SGMII_REMOTE_FAULT_DIS;
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regmap_write(eth->sgmiisys, SGMSYS_SGMII_MODE, val);
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if (MTK_HAS_CAPS(eth->soc->caps, MTK_GMAC_SHARED_SGMII))
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sid = 0;
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else
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sid = mac_id;
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regmap_read(eth->sgmiisys, SGMSYS_PCS_CONTROL_1, &val);
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val |= SGMII_AN_RESTART;
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regmap_write(eth->sgmiisys, SGMSYS_PCS_CONTROL_1, val);
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if (MTK_HAS_FLAGS(eth->sgmii->flags[sid], MTK_SGMII_PHYSPEED_AN))
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err = mtk_sgmii_setup_mode_an(eth->sgmii, sid);
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else
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err = mtk_sgmii_setup_mode_force(eth->sgmii, sid);
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regmap_read(eth->sgmiisys, SGMSYS_QPHY_PWR_STATE_CTRL, &val);
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val &= ~SGMII_PHYA_PWD;
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regmap_write(eth->sgmiisys, SGMSYS_QPHY_PWR_STATE_CTRL, val);
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if (err)
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return err;
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/* Determine MUX for which GMAC uses the SGMII interface */
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if (MTK_HAS_CAPS(eth->soc->caps, MTK_DUAL_GMAC_SHARED_SGMII)) {
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regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
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val &= ~SYSCFG0_SGMII_MASK;
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val |= !mac_id ? SYSCFG0_SGMII_GMAC1 : SYSCFG0_SGMII_GMAC2;
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regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
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dev_info(eth->dev, "setup shared sgmii for gmac=%d\n",
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mac_id);
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}
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regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
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if (!mac_id)
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val |= SYSCFG0_SGMII_GMAC1;
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else
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val |= MTK_HAS_CAPS(eth->soc->caps, MTK_GMAC_SHARED_SGMII) ?
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SYSCFG0_SGMII_GMAC2 : SYSCFG0_SGMII_GMAC2_V2;
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regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
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/* Setup the GMAC1 going through SGMII path when SoC also support
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* ESW on GMAC1
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@ -204,6 +205,8 @@ static void mtk_gmac_sgmii_hw_setup(struct mtk_eth *eth, int mac_id)
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mtk_w32(eth, 0, MTK_MAC_MISC);
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dev_info(eth->dev, "setup gmac1 going through sgmii");
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}
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return 0;
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}
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static void mtk_phy_link_adjust(struct net_device *dev)
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@ -295,6 +298,7 @@ static int mtk_phy_connect(struct net_device *dev)
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struct mtk_eth *eth;
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struct device_node *np;
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u32 val;
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int err;
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eth = mac->hw;
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np = of_parse_phandle(mac->of_node, "phy-handle", 0);
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@ -314,8 +318,11 @@ static int mtk_phy_connect(struct net_device *dev)
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case PHY_INTERFACE_MODE_RGMII:
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break;
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case PHY_INTERFACE_MODE_SGMII:
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if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII))
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mtk_gmac_sgmii_hw_setup(eth, mac->id);
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if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
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err = mtk_gmac_sgmii_hw_setup(eth, mac->id);
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if (err)
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goto err_phy;
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}
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break;
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case PHY_INTERFACE_MODE_MII:
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mac->ge_mode = 1;
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@ -2483,13 +2490,16 @@ static int mtk_probe(struct platform_device *pdev)
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}
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if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
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eth->sgmiisys =
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syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
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"mediatek,sgmiisys");
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if (IS_ERR(eth->sgmiisys)) {
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dev_err(&pdev->dev, "no sgmiisys regmap found\n");
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return PTR_ERR(eth->sgmiisys);
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}
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eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii),
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GFP_KERNEL);
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if (!eth->sgmii)
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return -ENOMEM;
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err = mtk_sgmii_init(eth->sgmii, pdev->dev.of_node,
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eth->soc->ana_rgc3);
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if (err)
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return err;
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}
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if (eth->soc->required_pctl) {
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@ -2642,7 +2652,8 @@ static const struct mtk_soc_data mt7621_data = {
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};
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static const struct mtk_soc_data mt7622_data = {
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.caps = MTK_DUAL_GMAC_SHARED_SGMII | MTK_GMAC1_ESW | MTK_HWLRO,
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.ana_rgc3 = 0x2028,
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.caps = MTK_GMAC_SHARED_SGMII | MTK_GMAC1_ESW | MTK_HWLRO,
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.required_clks = MT7622_CLKS_BITMAP,
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.required_pctl = false,
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};
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@ -15,6 +15,10 @@
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#ifndef MTK_ETH_H
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#define MTK_ETH_H
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#include <linux/dma-mapping.h>
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#include <linux/netdevice.h>
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#include <linux/of_net.h>
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#include <linux/u64_stats_sync.h>
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#include <linux/refcount.h>
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#define MTK_QDMA_PAGE_SIZE 2048
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@ -372,6 +376,7 @@
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#define SYSCFG0_SGMII_MASK (3 << 8)
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#define SYSCFG0_SGMII_GMAC1 ((2 << 8) & GENMASK(9, 8))
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#define SYSCFG0_SGMII_GMAC2 ((3 << 8) & GENMASK(9, 8))
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#define SYSCFG0_SGMII_GMAC2_V2 ((1 << 8) & GENMASK(9, 8))
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/* ethernet subsystem clock register */
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#define ETHSYS_CLKCFG0 0x2c
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@ -567,7 +572,7 @@ struct mtk_rx_ring {
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#define MTK_SGMII BIT(8)
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#define MTK_GMAC1_SGMII (BIT(9) | MTK_SGMII)
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#define MTK_GMAC2_SGMII (BIT(10) | MTK_SGMII)
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#define MTK_DUAL_GMAC_SHARED_SGMII (BIT(11) | MTK_GMAC1_SGMII | \
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#define MTK_GMAC_SHARED_SGMII (BIT(11) | MTK_GMAC1_SGMII | \
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MTK_GMAC2_SGMII)
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#define MTK_HWLRO BIT(12)
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#define MTK_SHARED_INT BIT(13)
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@ -575,6 +580,8 @@ struct mtk_rx_ring {
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/* struct mtk_eth_data - This is the structure holding all differences
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* among various plaforms
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* @ana_rgc3: The offset for register ANA_RGC3 related to
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* sgmiisys syscon
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* @caps Flags shown the extra capability for the SoC
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* @required_clks Flags shown the bitmap for required clocks on
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* the target SoC
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@ -582,6 +589,7 @@ struct mtk_rx_ring {
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* the extra setup for those pins used by GMAC.
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*/
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struct mtk_soc_data {
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u32 ana_rgc3;
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u32 caps;
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u32 required_clks;
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bool required_pctl;
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@ -590,6 +598,26 @@ struct mtk_soc_data {
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/* currently no SoC has more than 2 macs */
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#define MTK_MAX_DEVS 2
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#define MTK_SGMII_PHYSPEED_AN BIT(31)
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#define MTK_SGMII_PHYSPEED_MASK GENMASK(0, 2)
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#define MTK_SGMII_PHYSPEED_1000 BIT(0)
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#define MTK_SGMII_PHYSPEED_2500 BIT(1)
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#define MTK_HAS_FLAGS(flags, _x) (((flags) & (_x)) == (_x))
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/* struct mtk_sgmii - This is the structure holding sgmii regmap and its
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* characteristics
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* @regmap: The register map pointing at the range used to setup
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* SGMII modes
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* @flags: The enum refers to which mode the sgmii wants to run on
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* @ana_rgc3: The offset refers to register ANA_RGC3 related to regmap
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*/
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struct mtk_sgmii {
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struct regmap *regmap[MTK_MAX_DEVS];
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u32 flags[MTK_MAX_DEVS];
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u32 ana_rgc3;
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};
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/* struct mtk_eth - This is the main datasructure for holding the state
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* of the driver
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* @dev: The device pointer
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@ -605,8 +633,6 @@ struct mtk_soc_data {
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* @msg_enable: Ethtool msg level
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* @ethsys: The register map pointing at the range used to setup
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* MII modes
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* @sgmiisys: The register map pointing at the range used to setup
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* SGMII modes
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* @pctl: The register map pointing at the range used to setup
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* GMAC port drive/slew values
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* @dma_refcnt: track how many netdevs are using the DMA engine
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@ -638,7 +664,7 @@ struct mtk_eth {
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u32 msg_enable;
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unsigned long sysclk;
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struct regmap *ethsys;
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struct regmap *sgmiisys;
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struct mtk_sgmii *sgmii;
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struct regmap *pctl;
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bool hwlro;
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refcount_t dma_refcnt;
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@ -689,4 +715,9 @@ void mtk_stats_update_mac(struct mtk_mac *mac);
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void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
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u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
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int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np,
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u32 ana_rgc3);
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int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id);
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int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id);
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#endif /* MTK_ETH_H */
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105
drivers/net/ethernet/mediatek/mtk_sgmii.c
Normal file
105
drivers/net/ethernet/mediatek/mtk_sgmii.c
Normal file
@ -0,0 +1,105 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2018-2019 MediaTek Inc.
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/* A library for MediaTek SGMII circuit
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*
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* Author: Sean Wang <sean.wang@mediatek.com>
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*
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*/
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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#include <linux/regmap.h>
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#include "mtk_eth_soc.h"
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int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *r, u32 ana_rgc3)
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{
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struct device_node *np;
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const char *str;
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int i, err;
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ss->ana_rgc3 = ana_rgc3;
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for (i = 0; i < MTK_MAX_DEVS; i++) {
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np = of_parse_phandle(r, "mediatek,sgmiisys", i);
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if (!np)
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break;
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ss->regmap[i] = syscon_node_to_regmap(np);
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if (IS_ERR(ss->regmap[i]))
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return PTR_ERR(ss->regmap[i]);
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err = of_property_read_string(np, "mediatek,physpeed", &str);
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if (err)
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return err;
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if (!strcmp(str, "2500"))
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ss->flags[i] |= MTK_SGMII_PHYSPEED_2500;
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else if (!strcmp(str, "1000"))
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ss->flags[i] |= MTK_SGMII_PHYSPEED_1000;
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else if (!strcmp(str, "auto"))
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ss->flags[i] |= MTK_SGMII_PHYSPEED_AN;
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else
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return -EINVAL;
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}
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return 0;
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}
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int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id)
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{
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unsigned int val;
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if (!ss->regmap[id])
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return -EINVAL;
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/* Setup the link timer and QPHY power up inside SGMIISYS */
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regmap_write(ss->regmap[id], SGMSYS_PCS_LINK_TIMER,
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SGMII_LINK_TIMER_DEFAULT);
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regmap_read(ss->regmap[id], SGMSYS_SGMII_MODE, &val);
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val |= SGMII_REMOTE_FAULT_DIS;
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regmap_write(ss->regmap[id], SGMSYS_SGMII_MODE, val);
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regmap_read(ss->regmap[id], SGMSYS_PCS_CONTROL_1, &val);
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val |= SGMII_AN_RESTART;
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regmap_write(ss->regmap[id], SGMSYS_PCS_CONTROL_1, val);
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regmap_read(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, &val);
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val &= ~SGMII_PHYA_PWD;
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regmap_write(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, val);
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return 0;
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}
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int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id)
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{
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unsigned int val;
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int mode;
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if (!ss->regmap[id])
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return -EINVAL;
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regmap_read(ss->regmap[id], ss->ana_rgc3, &val);
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val &= ~GENMASK(2, 3);
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mode = ss->flags[id] & MTK_SGMII_PHYSPEED_MASK;
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val |= (mode == MTK_SGMII_PHYSPEED_1000) ? 0 : BIT(2);
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regmap_write(ss->regmap[id], ss->ana_rgc3, val);
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/* Disable SGMII AN */
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regmap_read(ss->regmap[id], SGMSYS_PCS_CONTROL_1, &val);
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val &= ~BIT(12);
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regmap_write(ss->regmap[id], SGMSYS_PCS_CONTROL_1, val);
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/* SGMII force mode setting */
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val = 0x31120019;
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regmap_write(ss->regmap[id], SGMSYS_SGMII_MODE, val);
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/* Release PHYA power down state */
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regmap_read(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, &val);
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val &= ~SGMII_PHYA_PWD;
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regmap_write(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, val);
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return 0;
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}
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