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ARM: pmu: add support for interrupt-affinity property
Historically, the PMU devicetree bindings have expected SPIs to be listed in order of *logical* CPU number. This is problematic for bootloaders, especially when the boot CPU (logical ID 0) isn't listed first in the devicetree. This patch adds a new optional property, interrupt-affinity, to the PMU node which allows the interrupt affinity to be described using a list of phandled to CPU nodes, with each entry in the list corresponding to the SPI at the same index in the interrupts property. Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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@ -92,6 +92,7 @@ struct pmu_hw_events {
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struct arm_pmu {
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struct pmu pmu;
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cpumask_t active_irqs;
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int *irq_affinity;
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char *name;
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irqreturn_t (*handle_irq)(int irq_num, void *dev);
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void (*enable)(struct perf_event *event);
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@ -92,11 +92,16 @@ static void cpu_pmu_free_irq(struct arm_pmu *cpu_pmu)
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free_percpu_irq(irq, &hw_events->percpu_pmu);
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} else {
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for (i = 0; i < irqs; ++i) {
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if (!cpumask_test_and_clear_cpu(i, &cpu_pmu->active_irqs))
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int cpu = i;
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if (cpu_pmu->irq_affinity)
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cpu = cpu_pmu->irq_affinity[i];
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if (!cpumask_test_and_clear_cpu(cpu, &cpu_pmu->active_irqs))
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continue;
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irq = platform_get_irq(pmu_device, i);
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if (irq >= 0)
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free_irq(irq, per_cpu_ptr(&hw_events->percpu_pmu, i));
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free_irq(irq, per_cpu_ptr(&hw_events->percpu_pmu, cpu));
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}
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}
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}
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@ -128,32 +133,37 @@ static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler)
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on_each_cpu(cpu_pmu_enable_percpu_irq, &irq, 1);
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} else {
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for (i = 0; i < irqs; ++i) {
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int cpu = i;
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err = 0;
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irq = platform_get_irq(pmu_device, i);
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if (irq < 0)
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continue;
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if (cpu_pmu->irq_affinity)
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cpu = cpu_pmu->irq_affinity[i];
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/*
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* If we have a single PMU interrupt that we can't shift,
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* assume that we're running on a uniprocessor machine and
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* continue. Otherwise, continue without this interrupt.
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*/
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if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
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if (irq_set_affinity(irq, cpumask_of(cpu)) && irqs > 1) {
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pr_warn("unable to set irq affinity (irq=%d, cpu=%u)\n",
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irq, i);
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irq, cpu);
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continue;
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}
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err = request_irq(irq, handler,
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IRQF_NOBALANCING | IRQF_NO_THREAD, "arm-pmu",
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per_cpu_ptr(&hw_events->percpu_pmu, i));
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per_cpu_ptr(&hw_events->percpu_pmu, cpu));
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if (err) {
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pr_err("unable to request IRQ%d for ARM PMU counters\n",
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irq);
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return err;
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}
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cpumask_set_cpu(i, &cpu_pmu->active_irqs);
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cpumask_set_cpu(cpu, &cpu_pmu->active_irqs);
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}
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}
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@ -291,6 +301,48 @@ static int probe_current_pmu(struct arm_pmu *pmu)
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return ret;
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}
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static int of_pmu_irq_cfg(struct platform_device *pdev)
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{
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int i;
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int *irqs = kcalloc(pdev->num_resources, sizeof(*irqs), GFP_KERNEL);
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if (!irqs)
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return -ENOMEM;
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for (i = 0; i < pdev->num_resources; ++i) {
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struct device_node *dn;
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int cpu;
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dn = of_parse_phandle(pdev->dev.of_node, "interrupt-affinity",
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i);
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if (!dn) {
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pr_warn("Failed to parse %s/interrupt-affinity[%d]\n",
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of_node_full_name(dn), i);
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break;
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}
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for_each_possible_cpu(cpu)
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if (arch_find_n_match_cpu_physical_id(dn, cpu, NULL))
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break;
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of_node_put(dn);
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if (cpu >= nr_cpu_ids) {
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pr_warn("Failed to find logical CPU for %s\n",
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dn->name);
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break;
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}
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irqs[i] = cpu;
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}
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if (i == pdev->num_resources)
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cpu_pmu->irq_affinity = irqs;
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else
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kfree(irqs);
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return 0;
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}
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static int cpu_pmu_device_probe(struct platform_device *pdev)
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{
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const struct of_device_id *of_id;
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@ -315,7 +367,10 @@ static int cpu_pmu_device_probe(struct platform_device *pdev)
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if (node && (of_id = of_match_node(cpu_pmu_of_device_ids, pdev->dev.of_node))) {
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init_fn = of_id->data;
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ret = init_fn(pmu);
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ret = of_pmu_irq_cfg(pdev);
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if (!ret)
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ret = init_fn(pmu);
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} else {
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ret = probe_current_pmu(pmu);
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}
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