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pinctrl: mediatek: don't hardcode mode encoding in common code

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MT8365 encode the pins mode differently than other
MTK pinctrl drivers that use the PINCTRL_MTK common code.

Add 3 new fields in mtk_pinctrl_devdata in order to store how
pin modes are encoded into the register. At the
same time update all the pinctrl driver that depends on
CONFIG_PINCTRL_MTK.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Link: https://lore.kernel.org/r/20210519162409.3755679-2-fparent@baylibre.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Fabien Parent 2021-05-19 18:24:07 +02:00 committed by Linus Walleij
parent 8b4c397d88
commit 9f940d8ecf
10 changed files with 36 additions and 10 deletions
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3
drivers/pinctrl/mediatek/pinctrl-mt2701.c
View File

@ -523,6 +523,9 @@ static const struct mtk_pinctrl_devdata mt2701_pinctrl_data = {
.port_shf = 4,
.port_mask = 0x1f,
.port_align = 4,
.mode_mask = 0xf,
.mode_per_reg = 5,
.mode_shf = 4,
.eint_hw = {
.port_mask = 6,
.ports = 6,

3
drivers/pinctrl/mediatek/pinctrl-mt2712.c
View File

@ -576,6 +576,9 @@ static const struct mtk_pinctrl_devdata mt2712_pinctrl_data = {
.port_shf = 4,
.port_mask = 0xf,
.port_align = 4,
.mode_mask = 0xf,
.mode_per_reg = 5,
.mode_shf = 4,
.eint_hw = {
.port_mask = 0xf,
.ports = 8,

3
drivers/pinctrl/mediatek/pinctrl-mt6397.c
View File

@ -33,6 +33,9 @@ static const struct mtk_pinctrl_devdata mt6397_pinctrl_data = {
.port_shf = 3,
.port_mask = 0x3,
.port_align = 2,
.mode_mask = 0xf,
.mode_per_reg = 5,
.mode_shf = 4,
};
static int mt6397_pinctrl_probe(struct platform_device *pdev)

3
drivers/pinctrl/mediatek/pinctrl-mt8127.c
View File

@ -292,6 +292,9 @@ static const struct mtk_pinctrl_devdata mt8127_pinctrl_data = {
.port_shf = 4,
.port_mask = 0xf,
.port_align = 4,
.mode_mask = 0xf,
.mode_per_reg = 5,
.mode_shf = 4,
.eint_hw = {
.port_mask = 7,
.ports = 6,

3
drivers/pinctrl/mediatek/pinctrl-mt8135.c
View File

@ -305,6 +305,9 @@ static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = {
.port_shf = 4,
.port_mask = 0xf,
.port_align = 4,
.mode_mask = 0xf,
.mode_per_reg = 5,
.mode_shf = 4,
.eint_hw = {
.port_mask = 7,
.ports = 6,

3
drivers/pinctrl/mediatek/pinctrl-mt8167.c
View File

@ -324,6 +324,9 @@ static const struct mtk_pinctrl_devdata mt8167_pinctrl_data = {
.port_shf = 4,
.port_mask = 0xf,
.port_align = 4,
.mode_mask = 0xf,
.mode_per_reg = 5,
.mode_shf = 4,
.eint_hw = {
.port_mask = 7,
.ports = 6,

3
drivers/pinctrl/mediatek/pinctrl-mt8173.c
View File

@ -332,6 +332,9 @@ static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = {
.port_shf = 4,
.port_mask = 0xf,
.port_align = 4,
.mode_mask = 0xf,
.mode_per_reg = 5,
.mode_shf = 4,
.eint_hw = {
.port_mask = 7,
.ports = 6,

3
drivers/pinctrl/mediatek/pinctrl-mt8516.c
View File

@ -324,6 +324,9 @@ static const struct mtk_pinctrl_devdata mt8516_pinctrl_data = {
.port_shf = 4,
.port_mask = 0xf,
.port_align = 4,
.mode_mask = 0xf,
.mode_per_reg = 5,
.mode_shf = 4,
.eint_hw = {
.port_mask = 7,
.ports = 6,

19
drivers/pinctrl/mediatek/pinctrl-mtk-common.c
View File

@ -33,7 +33,6 @@
#include "mtk-eint.h"
#include "pinctrl-mtk-common.h"
#define MAX_GPIO_MODE_PER_REG 5
#define GPIO_MODE_BITS 3
#define GPIO_MODE_PREFIX "GPIO"
@ -61,7 +60,7 @@ static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl,
static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin)
{
/* Different SoC has different mask and port shift. */
return ((pin >> 4) & pctl->devdata->port_mask)
return ((pin >> pctl->devdata->mode_shf) & pctl->devdata->port_mask)
<< pctl->devdata->port_shf;
}
@ -74,7 +73,7 @@ static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
bit = BIT(offset & 0xf);
bit = BIT(offset & pctl->devdata->mode_mask);
if (pctl->devdata->spec_dir_set)
pctl->devdata->spec_dir_set(&reg_addr, offset);
@ -96,7 +95,7 @@ static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset;
bit = BIT(offset & 0xf);
bit = BIT(offset & pctl->devdata->mode_mask);
if (value)
reg_addr = SET_ADDR(reg_addr, pctl);
@ -135,7 +134,7 @@ static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin,
pin, pctl->devdata->port_align, value, arg);
}
bit = BIT(pin & 0xf);
bit = BIT(offset & pctl->devdata->mode_mask);
if (arg == PIN_CONFIG_INPUT_ENABLE)
offset = pctl->devdata->ies_offset;
@ -311,7 +310,7 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
return -EINVAL;
}
bit = BIT(pin & 0xf);
bit = BIT(pin & pctl->devdata->mode_mask);
if (enable)
reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) +
pctl->devdata->pullen_offset, pctl);
@ -683,11 +682,11 @@ static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev,
pctl->devdata->spec_pinmux_set(mtk_get_regmap(pctl, pin),
pin, mode);
reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << pctl->devdata->port_shf)
reg_addr = ((pin / pctl->devdata->mode_per_reg) << pctl->devdata->port_shf)
+ pctl->devdata->pinmux_offset;
mode &= mask;
bit = pin % MAX_GPIO_MODE_PER_REG;
bit = pin % pctl->devdata->mode_per_reg;
mask <<= (GPIO_MODE_BITS * bit);
val = (mode << (GPIO_MODE_BITS * bit));
return regmap_update_bits(mtk_get_regmap(pctl, pin),
@ -798,7 +797,7 @@ static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
bit = BIT(offset & 0xf);
bit = BIT(offset & pctl->devdata->mode_mask);
if (pctl->devdata->spec_dir_set)
pctl->devdata->spec_dir_set(&reg_addr, offset);
@ -820,7 +819,7 @@ static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset)
reg_addr = mtk_get_port(pctl, offset) +
pctl->devdata->din_offset;
bit = BIT(offset & 0xf);
bit = BIT(offset & pctl->devdata->mode_mask);
regmap_read(pctl->regmap1, reg_addr, &read_val);
return !!(read_val & bit);
}

3
drivers/pinctrl/mediatek/pinctrl-mtk-common.h
View File

@ -254,6 +254,9 @@ struct mtk_pinctrl_devdata {
unsigned char port_align;
struct mtk_eint_hw eint_hw;
struct mtk_eint_regs *eint_regs;
unsigned int mode_mask;
unsigned int mode_per_reg;
unsigned int mode_shf;
};
struct mtk_pinctrl {