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sh: cpu dma evt2irq migration.

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This migrates the cpu-family relative DMA IRQ definitions over to
evt2irq() backed hwirq lookups.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt 2012-05-18 17:27:28 +09:00
parent 6b1ef625c3
commit 9f38045643
3 changed files with 57 additions and 50 deletions
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6
arch/sh/include/cpu-sh3/cpu/dma.h
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@ -1,6 +1,8 @@
#ifndef __ASM_CPU_SH3_DMA_H
#define __ASM_CPU_SH3_DMA_H
#include <linux/sh_intc.h>
#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
defined(CONFIG_CPU_SUBTYPE_SH7721) || \
defined(CONFIG_CPU_SUBTYPE_SH7710) || \
@ -10,8 +12,8 @@
#define SH_DMAC_BASE0 0xa4000020
#endif
#define DMTE0_IRQ 48
#define DMTE4_IRQ 76
#define DMTE0_IRQ evt2irq(0x800)
#define DMTE4_IRQ evt2irq(0xb80)
/* Definitions for the SuperH DMAC */
#define TM_BURST 0x00000020

90
arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
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@ -1,75 +1,77 @@
#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H
#define __ASM_SH_CPU_SH4_DMA_SH7780_H
#include <linux/sh_intc.h>
#if defined(CONFIG_CPU_SUBTYPE_SH7343) || \
defined(CONFIG_CPU_SUBTYPE_SH7730)
#define DMTE0_IRQ 48
#define DMTE4_IRQ 76
#define DMAE0_IRQ 78 /* DMA Error IRQ*/
#define DMTE0_IRQ evt2irq(0x800)
#define DMTE4_IRQ evt2irq(0xb80)
#define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
#define SH_DMAC_BASE0 0xFE008020
#define SH_DMARS_BASE0 0xFE009000
#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
#define DMTE0_IRQ 48
#define DMTE4_IRQ 76
#define DMAE0_IRQ 78 /* DMA Error IRQ*/
#define DMTE0_IRQ evt2irq(0x800)
#define DMTE4_IRQ evt2irq(0xb80)
#define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
#define SH_DMAC_BASE0 0xFE008020
#define SH_DMARS_BASE0 0xFE009000
#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
defined(CONFIG_CPU_SUBTYPE_SH7764)
#define DMTE0_IRQ 34
#define DMTE4_IRQ 44
#define DMAE0_IRQ 38
#define DMTE0_IRQ evt2irq(0x640)
#define DMTE4_IRQ evt2irq(0x780)
#define DMAE0_IRQ evt2irq(0x6c0)
#define SH_DMAC_BASE0 0xFF608020
#define SH_DMARS_BASE0 0xFF609000
#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
#define DMTE0_IRQ 48 /* DMAC0A*/
#define DMTE4_IRQ 76 /* DMAC0B */
#define DMTE6_IRQ 40
#define DMTE8_IRQ 42 /* DMAC1A */
#define DMTE9_IRQ 43
#define DMTE10_IRQ 72 /* DMAC1B */
#define DMTE11_IRQ 73
#define DMAE0_IRQ 78 /* DMA Error IRQ*/
#define DMAE1_IRQ 74 /* DMA Error IRQ*/
#define DMTE0_IRQ evt2irq(0x800) /* DMAC0A*/
#define DMTE4_IRQ evt2irq(0xb80) /* DMAC0B */
#define DMTE6_IRQ evt2irq(0x700)
#define DMTE8_IRQ evt2irq(0x740) /* DMAC1A */
#define DMTE9_IRQ evt2irq(0x760)
#define DMTE10_IRQ evt2irq(0xb00) /* DMAC1B */
#define DMTE11_IRQ evt2irq(0xb20)
#define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
#define DMAE1_IRQ evt2irq(0xb40) /* DMA Error IRQ*/
#define SH_DMAC_BASE0 0xFE008020
#define SH_DMAC_BASE1 0xFDC08020
#define SH_DMARS_BASE0 0xFDC09000
#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
#define DMTE0_IRQ 48 /* DMAC0A*/
#define DMTE4_IRQ 76 /* DMAC0B */
#define DMTE6_IRQ 40
#define DMTE8_IRQ 42 /* DMAC1A */
#define DMTE9_IRQ 43
#define DMTE10_IRQ 72 /* DMAC1B */
#define DMTE11_IRQ 73
#define DMAE0_IRQ 78 /* DMA Error IRQ*/
#define DMAE1_IRQ 74 /* DMA Error IRQ*/
#define DMTE0_IRQ evt2irq(0x800) /* DMAC0A*/
#define DMTE4_IRQ evt2irq(0xb80) /* DMAC0B */
#define DMTE6_IRQ evt2irq(0x700)
#define DMTE8_IRQ evt2irq(0x740) /* DMAC1A */
#define DMTE9_IRQ evt2irq(0x760)
#define DMTE10_IRQ evt2irq(0xb00) /* DMAC1B */
#define DMTE11_IRQ evt2irq(0xb20)
#define DMAE0_IRQ evt2irq(0xbc0) /* DMA Error IRQ*/
#define DMAE1_IRQ evt2irq(0xb40) /* DMA Error IRQ*/
#define SH_DMAC_BASE0 0xFE008020
#define SH_DMAC_BASE1 0xFDC08020
#define SH_DMARS_BASE0 0xFE009000
#define SH_DMARS_BASE1 0xFDC09000
#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
#define DMTE0_IRQ 34
#define DMTE4_IRQ 44
#define DMTE6_IRQ 46
#define DMTE8_IRQ 92
#define DMTE9_IRQ 93
#define DMTE10_IRQ 94
#define DMTE11_IRQ 95
#define DMAE0_IRQ 38 /* DMA Error IRQ */
#define DMTE0_IRQ evt2irq(0x640)
#define DMTE4_IRQ evt2irq(0x780)
#define DMTE6_IRQ evt2irq(0x7c0)
#define DMTE8_IRQ evt2irq(0xd80)
#define DMTE9_IRQ evt2irq(0xda0)
#define DMTE10_IRQ evt2irq(0xdc0)
#define DMTE11_IRQ evt2irq(0xde0)
#define DMAE0_IRQ evt2irq(0x6c0) /* DMA Error IRQ */
#define SH_DMAC_BASE0 0xFC808020
#define SH_DMAC_BASE1 0xFC818020
#define SH_DMARS_BASE0 0xFC809000
#else /* SH7785 */
#define DMTE0_IRQ 33
#define DMTE4_IRQ 37
#define DMTE6_IRQ 52
#define DMTE8_IRQ 54
#define DMTE9_IRQ 55
#define DMTE10_IRQ 56
#define DMTE11_IRQ 57
#define DMAE0_IRQ 39 /* DMA Error IRQ0 */
#define DMAE1_IRQ 58 /* DMA Error IRQ1 */
#define DMTE0_IRQ evt2irq(0x620)
#define DMTE4_IRQ evt2irq(0x6a0)
#define DMTE6_IRQ evt2irq(0x880)
#define DMTE8_IRQ evt2irq(0x8c0)
#define DMTE9_IRQ evt2irq(0x8e0)
#define DMTE10_IRQ evt2irq(0x900)
#define DMTE11_IRQ evt2irq(0x920)
#define DMAE0_IRQ evt2irq(0x6e0) /* DMA Error IRQ0 */
#define DMAE1_IRQ evt2irq(0x940) /* DMA Error IRQ1 */
#define SH_DMAC_BASE0 0xFC808020
#define SH_DMAC_BASE1 0xFCC08020
#define SH_DMARS_BASE0 0xFC809000

11
arch/sh/include/cpu-sh4/cpu/dma.h
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@ -8,13 +8,16 @@
#include <cpu/dma-sh4a.h>
#else /* CONFIG_CPU_SH4A */
#include <linux/sh_intc.h>
/*
* SH7750/SH7751/SH7760
*/
#define DMTE0_IRQ 34
#define DMTE4_IRQ 44
#define DMTE6_IRQ 46
#define DMAE0_IRQ 38
#define DMTE0_IRQ evt2irq(0x640)
#define DMTE4_IRQ evt2irq(0x780)
#define DMTE6_IRQ evt2irq(0x7c0)
#define DMAE0_IRQ evt2irq(0x6c0)
#define SH_DMAC_BASE0 0xffa00000
#define SH_DMAC_BASE1 0xffa00070