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ARM: EXYNOS: Enable MDMA driver

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This patch adds MDMA platform data and enables
MDMA for DMA memcpy operation for EXYNOS SoCs.

Signed-off-by: Boojin Kim <boojin.kim@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Boojin Kim 2012-02-15 13:15:12 +09:00 committed by Kukjin Kim
parent 44b2cef5ae
commit 9ed76e0336
5 changed files with 42 additions and 1 deletions
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8
arch/arm/mach-exynos/clock-exynos4.c
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@ -784,6 +784,13 @@ static struct clk exynos4_clk_pdma1 = {
.ctrlbit = (1 << 1), .ctrlbit = (1 << 1),
}; };
static struct clk exynos4_clk_mdma1 = {
.name = "dma",
.devname = "dma-pl330.2",
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = ((1 << 8) | (1 << 5) | (1 << 2)),
};
struct clk *exynos4_clkset_group_list[] = { struct clk *exynos4_clkset_group_list[] = {
[0] = &clk_ext_xtal_mux, [0] = &clk_ext_xtal_mux,
[1] = &clk_xusbxti, [1] = &clk_xusbxti,
@ -1302,6 +1309,7 @@ static struct clksrc_clk *exynos4_sysclks[] = {
static struct clk *exynos4_clk_cdev[] = { static struct clk *exynos4_clk_cdev[] = {
&exynos4_clk_pdma0, &exynos4_clk_pdma0,
&exynos4_clk_pdma1, &exynos4_clk_pdma1,
&exynos4_clk_mdma1,
}; };
static struct clksrc_clk *exynos4_clksrc_cdev[] = { static struct clksrc_clk *exynos4_clksrc_cdev[] = {

22
arch/arm/mach-exynos/dma.c
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@ -113,6 +113,25 @@ static struct dma_pl330_platdata exynos4_pdma1_pdata = {
static AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330, static AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330,
EXYNOS4_PA_PDMA1, {IRQ_PDMA1}, &exynos4_pdma1_pdata); EXYNOS4_PA_PDMA1, {IRQ_PDMA1}, &exynos4_pdma1_pdata);
static u8 mdma_peri[] = {
DMACH_MTOM_0,
DMACH_MTOM_1,
DMACH_MTOM_2,
DMACH_MTOM_3,
DMACH_MTOM_4,
DMACH_MTOM_5,
DMACH_MTOM_6,
DMACH_MTOM_7,
};
static struct dma_pl330_platdata exynos4_mdma1_pdata = {
.nr_valid_peri = ARRAY_SIZE(mdma_peri),
.peri_id = mdma_peri,
};
static AMBA_AHB_DEVICE(exynos4_mdma1, "dma-pl330.2", 0x00041330,
EXYNOS4_PA_MDMA1, {IRQ_MDMA1}, &exynos4_mdma1_pdata);
static int __init exynos4_dma_init(void) static int __init exynos4_dma_init(void)
{ {
if (of_have_populated_dt()) if (of_have_populated_dt())
@ -126,6 +145,9 @@ static int __init exynos4_dma_init(void)
dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask); dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);
amba_device_register(&exynos4_pdma1_device, &iomem_resource); amba_device_register(&exynos4_pdma1_device, &iomem_resource);
dma_cap_set(DMA_MEMCPY, exynos4_mdma1_pdata.cap_mask);
amba_device_register(&exynos4_mdma1_device, &iomem_resource);
return 0; return 0;
} }
arch_initcall(exynos4_dma_init); arch_initcall(exynos4_dma_init);

2
arch/arm/mach-exynos/include/mach/irqs.h
View File

@ -43,6 +43,8 @@
#define IRQ_EINT15 IRQ_SPI(31) #define IRQ_EINT15 IRQ_SPI(31)
#define IRQ_EINT16_31 IRQ_SPI(32) #define IRQ_EINT16_31 IRQ_SPI(32)
#define IRQ_MDMA0 IRQ_SPI(33)
#define IRQ_MDMA1 IRQ_SPI(34)
#define IRQ_PDMA0 IRQ_SPI(35) #define IRQ_PDMA0 IRQ_SPI(35)
#define IRQ_PDMA1 IRQ_SPI(36) #define IRQ_PDMA1 IRQ_SPI(36)
#define IRQ_TIMER0_VIC IRQ_SPI(37) #define IRQ_TIMER0_VIC IRQ_SPI(37)

3
arch/arm/mach-exynos/include/mach/map.h
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@ -67,7 +67,8 @@
#define EXYNOS4_PA_TWD 0x10500600 #define EXYNOS4_PA_TWD 0x10500600
#define EXYNOS4_PA_L2CC 0x10502000 #define EXYNOS4_PA_L2CC 0x10502000
#define EXYNOS4_PA_MDMA 0x10810000 #define EXYNOS4_PA_MDMA0 0x10810000
#define EXYNOS4_PA_MDMA1 0x12840000
#define EXYNOS4_PA_PDMA0 0x12680000 #define EXYNOS4_PA_PDMA0 0x12680000
#define EXYNOS4_PA_PDMA1 0x12690000 #define EXYNOS4_PA_PDMA1 0x12690000

8
arch/arm/plat-samsung/include/plat/dma-pl330.h
View File

@ -82,6 +82,14 @@ enum dma_ch {
DMACH_SLIMBUS4_TX, DMACH_SLIMBUS4_TX,
DMACH_SLIMBUS5_RX, DMACH_SLIMBUS5_RX,
DMACH_SLIMBUS5_TX, DMACH_SLIMBUS5_TX,
DMACH_MTOM_0,
DMACH_MTOM_1,
DMACH_MTOM_2,
DMACH_MTOM_3,
DMACH_MTOM_4,
DMACH_MTOM_5,
DMACH_MTOM_6,
DMACH_MTOM_7,
/* END Marker, also used to denote a reserved channel */ /* END Marker, also used to denote a reserved channel */
DMACH_MAX, DMACH_MAX,
}; };