Minki/linux
1
0
Fork 1
mirror of https://github.com/torvalds/linux.git synced 2024-11-02 10:11:36 +00:00
Code Issues Packages Projects Releases Wiki Activity

generic GPIO support for the Freescale Coldfire 5249.

Browse Source 
Add support for the 5249.

Signed-off-by: Steven King <sfking@fdwdc.com>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
This commit is contained in:
sfking@fdwdc.com 2009-06-19 18:11:05 -07:00 committed by Greg Ungerer
parent a03ce7d9ef
commit 9e8ded166d
3 changed files with 80 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
arch/m68k/include/asm/m5249sim.h
View File

@ -73,14 +73,14 @@
/*
* General purpose IO registers (in MBAR2).
*/
#define MCFSIM2_GPIOREAD 0x0 /* GPIO read values */
#define MCFSIM2_GPIOWRITE 0x4 /* GPIO write values */
#define MCFSIM2_GPIOENABLE 0x8 /* GPIO enabled */
#define MCFSIM2_GPIOFUNC 0xc /* GPIO function */
#define MCFSIM2_GPIO1READ 0xb0 /* GPIO1 read values */
#define MCFSIM2_GPIO1WRITE 0xb4 /* GPIO1 write values */
#define MCFSIM2_GPIO1ENABLE 0xb8 /* GPIO1 enabled */
#define MCFSIM2_GPIO1FUNC 0xbc /* GPIO1 function */
#define MCFSIM2_GPIOREAD (MCF_MBAR2 + 0x000) /* GPIO read values */
#define MCFSIM2_GPIOWRITE (MCF_MBAR2 + 0x004) /* GPIO write values */
#define MCFSIM2_GPIOENABLE (MCF_MBAR2 + 0x008) /* GPIO enabled */
#define MCFSIM2_GPIOFUNC (MCF_MBAR2 + 0x00C) /* GPIO function */
#define MCFSIM2_GPIO1READ (MCF_MBAR2 + 0x0B0) /* GPIO1 read values */
#define MCFSIM2_GPIO1WRITE (MCF_MBAR2 + 0x0B4) /* GPIO1 write values */
#define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */
#define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */
#define MCFSIM2_GPIOINTSTAT 0xc0 /* GPIO interrupt status */
#define MCFSIM2_GPIOINTCLEAR 0xc0 /* GPIO interrupt clear */
@ -100,7 +100,12 @@
#define MCFSIM2_IDECONFIG1 0x18c /* IDEconfig1 */
#define MCFSIM2_IDECONFIG2 0x190 /* IDEconfig2 */
/*
* Generic GPIO support
*/
#define MCFGPIO_PIN_MAX 64
#define MCFGPIO_IRQ_MAX -1
#define MCFGPIO_IRQ_VECBASE -1
/*
* Macro to set IMR register. It is 32 bits on the 5249.
*/

2
arch/m68knommu/platform/5249/Makefile
View File

@ -14,5 +14,5 @@
asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
obj-y := config.o
obj-y := config.o gpio.o

65
arch/m68knommu/platform/5249/gpio.c Normal file
View File

@ -0,0 +1,65 @@
/*
* Coldfire generic GPIO support
*
* (C) Copyright 2009, Steven King <sfking@fdwdc.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/mcfgpio.h>
static struct mcf_gpio_chip mcf_gpio_chips[] = {
{
.gpio_chip = {
.label = "GPIO0",
.request = mcf_gpio_request,
.free = mcf_gpio_free,
.direction_input = mcf_gpio_direction_input,
.direction_output = mcf_gpio_direction_output,
.get = mcf_gpio_get_value,
.set = mcf_gpio_set_value,
.ngpio = 32,
},
.pddr = MCFSIM2_GPIOENABLE,
.podr = MCFSIM2_GPIOWRITE,
.ppdr = MCFSIM2_GPIOREAD,
},
{
.gpio_chip = {
.label = "GPIO1",
.request = mcf_gpio_request,
.free = mcf_gpio_free,
.direction_input = mcf_gpio_direction_input,
.direction_output = mcf_gpio_direction_output,
.get = mcf_gpio_get_value,
.set = mcf_gpio_set_value,
.base = 32,
.ngpio = 32,
},
.pddr = MCFSIM2_GPIO1ENABLE,
.podr = MCFSIM2_GPIO1WRITE,
.ppdr = MCFSIM2_GPIO1READ,
},
};
static int __init mcf_gpio_init(void)
{
unsigned i = 0;
while (i < ARRAY_SIZE(mcf_gpio_chips))
(void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
return 0;
}
core_initcall(mcf_gpio_init);