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math64, timers: Fix 32bit mul_u64_u32_shr() and friends
It turns out that while GCC-4.4 manages to generate 32x32->64 mult instructions for the 32bit mul_u64_u32_shr() code, any GCC after that fails horribly. Fix this by providing an explicit mul_u32_u32() function which can be architcture provided. Reported-by: Chris Metcalf <cmetcalf@mellanox.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Acked-by: Chris Metcalf <cmetcalf@mellanox.com> [for tile] Cc: Christopher S. Hall <christopher.s.hall@intel.com> Cc: David Gibson <david@gibson.dropbear.id.au> Cc: John Stultz <john.stultz@linaro.org> Cc: Laurent Vivier <lvivier@redhat.com> Cc: Liav Rehana <liavr@mellanox.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Parit Bhargava <prarit@redhat.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Richard Cochran <richardcochran@gmail.com> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/20161209083011.GD15765@worktop.programming.kicks-ass.net Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -5,7 +5,6 @@ generic-y += bug.h
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generic-y += bugs.h
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generic-y += clkdev.h
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generic-y += cputime.h
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generic-y += div64.h
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generic-y += emergency-restart.h
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generic-y += errno.h
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generic-y += exec.h
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14
arch/tile/include/asm/div64.h
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14
arch/tile/include/asm/div64.h
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@ -0,0 +1,14 @@
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#ifndef _ASM_TILE_DIV64_H
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#define _ASM_TILE_DIV64_H
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#ifdef __tilegx__
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static inline u64 mul_u32_u32(u32 a, u32 b)
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{
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return __insn_mul_lu_lu(a, b);
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}
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#define mul_u32_u32 mul_u32_u32
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#endif
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#include <asm-generic/div64.h>
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#endif /* _ASM_TILE_DIV64_H */
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@ -59,6 +59,17 @@ static inline u64 div_u64_rem(u64 dividend, u32 divisor, u32 *remainder)
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}
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#define div_u64_rem div_u64_rem
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static inline u64 mul_u32_u32(u32 a, u32 b)
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{
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u32 high, low;
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asm ("mull %[b]" : "=a" (low), "=d" (high)
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: [a] "a" (a), [b] "rm" (b) );
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return low | ((u64)high) << 32;
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}
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#define mul_u32_u32 mul_u32_u32
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#else
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# include <asm-generic/div64.h>
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#endif /* CONFIG_X86_32 */
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@ -133,6 +133,16 @@ __iter_div_u64_rem(u64 dividend, u32 divisor, u64 *remainder)
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return ret;
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}
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#ifndef mul_u32_u32
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/*
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* Many a GCC version messes this up and generates a 64x64 mult :-(
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*/
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static inline u64 mul_u32_u32(u32 a, u32 b)
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{
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return (u64)a * b;
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}
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#endif
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#if defined(CONFIG_ARCH_SUPPORTS_INT128) && defined(__SIZEOF_INT128__)
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#ifndef mul_u64_u32_shr
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@ -160,9 +170,9 @@ static inline u64 mul_u64_u32_shr(u64 a, u32 mul, unsigned int shift)
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al = a;
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ah = a >> 32;
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ret = ((u64)al * mul) >> shift;
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ret = mul_u32_u32(al, mul) >> shift;
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if (ah)
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ret += ((u64)ah * mul) << (32 - shift);
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ret += mul_u32_u32(ah, mul) << (32 - shift);
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return ret;
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}
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@ -186,10 +196,10 @@ static inline u64 mul_u64_u64_shr(u64 a, u64 b, unsigned int shift)
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a0.ll = a;
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b0.ll = b;
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rl.ll = (u64)a0.l.low * b0.l.low;
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rm.ll = (u64)a0.l.low * b0.l.high;
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rn.ll = (u64)a0.l.high * b0.l.low;
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rh.ll = (u64)a0.l.high * b0.l.high;
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rl.ll = mul_u32_u32(a0.l.low, b0.l.low);
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rm.ll = mul_u32_u32(a0.l.low, b0.l.high);
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rn.ll = mul_u32_u32(a0.l.high, b0.l.low);
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rh.ll = mul_u32_u32(a0.l.high, b0.l.high);
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/*
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* Each of these lines computes a 64-bit intermediate result into "c",
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@ -229,8 +239,8 @@ static inline u64 mul_u64_u32_div(u64 a, u32 mul, u32 divisor)
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} u, rl, rh;
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u.ll = a;
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rl.ll = (u64)u.l.low * mul;
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rh.ll = (u64)u.l.high * mul + rl.l.high;
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rl.ll = mul_u32_u32(u.l.low, mul);
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rh.ll = mul_u32_u32(u.l.high, mul) + rl.l.high;
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/* Bits 32-63 of the result will be in rh.l.low. */
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rl.l.high = do_div(rh.ll, divisor);
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