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drm/i915: Add i915 register dumping debugfs file
Add a debugfs file to dump the entire register range. Here we assume that reading write-only/reserved registers won't make the chip angry. Seems to hold true, thankfully. Signed-off-by: Ben Gamari <bgamari.foss@gmail.com> Signed-off-by: Eric Anholt <eric@anholt.net>
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@ -363,7 +363,37 @@ out:
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return 0;
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}
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static int i915_registers_info(struct seq_file *m, void *data) {
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struct drm_info_node *node = (struct drm_info_node *) m->private;
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struct drm_device *dev = node->minor->dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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uint32_t reg;
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#define DUMP_RANGE(start, end) \
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for (reg=start; reg < end; reg += 4) \
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seq_printf(m, "%08x\t%08x\n", reg, I915_READ(reg));
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DUMP_RANGE(0x00000, 0x00fff); /* VGA registers */
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DUMP_RANGE(0x02000, 0x02fff); /* instruction, memory, interrupt control registers */
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DUMP_RANGE(0x03000, 0x031ff); /* FENCE and PPGTT control registers */
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DUMP_RANGE(0x03200, 0x03fff); /* frame buffer compression registers */
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DUMP_RANGE(0x05000, 0x05fff); /* I/O control registers */
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DUMP_RANGE(0x06000, 0x06fff); /* clock control registers */
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DUMP_RANGE(0x07000, 0x07fff); /* 3D internal debug registers */
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DUMP_RANGE(0x07400, 0x088ff); /* GPE debug registers */
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DUMP_RANGE(0x0a000, 0x0afff); /* display palette registers */
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DUMP_RANGE(0x10000, 0x13fff); /* MMIO MCHBAR */
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DUMP_RANGE(0x30000, 0x3ffff); /* overlay registers */
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DUMP_RANGE(0x60000, 0x6ffff); /* display engine pipeline registers */
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DUMP_RANGE(0x70000, 0x72fff); /* display and cursor registers */
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DUMP_RANGE(0x73000, 0x73fff); /* performance counters */
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return 0;
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}
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static struct drm_info_list i915_debugfs_list[] = {
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{"i915_regs", i915_registers_info, 0},
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{"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
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{"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
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{"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
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